Obtaining a high refresh rate display using a low bandwidth digital interface

• US 20020075226A1
• Filed: 12/19/2000
• Published: 06/20/2002
• Est. Priority Date: 12/19/2000
• Status: Active Grant

• Current Assignee: Beijing Xiaomi Mobile Software Co., Ltd. (Xiaomi Corp.)
• Original Assignee: Louis A. Lippincott
• Inventors: Lippincott, Louis A.
• Granted Patent: US 6,756,996 B2
• Time in Patent Office: Days
• US Class Current: 345/156
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A sequence of input groups, each input group containing a number of input pixels, is received. A sequence of output frames is provided, where each output frame contains a number of output pixels to refresh a display screen. The pixels of each output frame include (1) a number of new pixels which are the input pixels of a respective input group, and (2) a number of old pixels which are the input pixels of a previous input group. The previous input group is one that'"'"'s received previous to the respective input group.

Claims

1. A method comprising:

receiving a sequence of input groups, each input group containing a plurality of input pixels; and

providing a sequence of output frames, each output frame containing a plurality of output pixels to refresh a display screen, wherein the pixels of each output frame include (1) a plurality of new pixels which are the input pixels of a respective input group, and (2) a plurality of old pixels which are the input pixels of a previous input group, the previous input group being an input group that is received previous to the respective input group.

2. The method of claim 1 wherein the previous input group is the input group that is received immediately prior to receiving the respective input group.

3. The method of claim 1 wherein the pixels of each output frame essentially consist of the plurality of new and old pixels.

4. The method of claim 3 wherein each input group has essentially one-half the number of pixels as an output frame.

5. The method of claim 4 wherein the sequence of input groups is received at a rate that is sufficiently high so as to allow the display screen to be refreshed at over 100 Hz.

6. The method of claim 3 wherein, if the pixels in each row of a frame were numbered 1,2,3, . . . , one half of the odd numbered pixels in each output frame are old pixels and one half are new pixels.

7. The method of claim 1 wherein the receiving and providing are performed in a display monitor, the sequence of input groups being received through a digital monitor interface of the display monitor.

8. The method of claim 1 wherein the receiving and providing operations are performed in a graphics component of a chipset, the sequence of input groups being received through a main memory interface of the chipset.

9. The method of claim 7 further comprising:

converting the sequence of output frames into analog form to drive one or more guns of a cathode ray tube (CRT) in the display monitor.

10. An article of manufacture comprising:

a digital interface to provide a digital sequence which includes a sequence of input groups;

a pixel extraction circuit coupled to the digital interface to extract a plurality of input pixels for each input group in the sequence of input groups;

a timing circuit coupled to the digital interface to determine a clock timing for activating elements of a display screen to display the input pixels;

a buffer coupled to the pixel extraction circuit, to store the plurality of input pixels for each input group in the sequence; and

a pixel multiplexer having a first input coupled to the pixel extraction circuit, a second input coupled to the buffer, and an output to provide a sequence of output frames, each output frame containing a plurality of output pixels taken from the first and second inputs as determined by the timing circuit, so that the pixels of each output frame include (1) a plurality of new pixels, received at the first input, which are the input pixels of a respective input group, and (2) a plurality of old pixels, received at the second input, which are the input pixels of a previous input group, the previous input group being an input group that is received, by the pixel extraction circuit, previous to the respective input group.

11. The article of manufacture of claim 10 wherein the buffer has a firstin-first-out structure to store and then deliver the input pixels.

12. The article of manufacture of claim 10 wherein the pixel extraction circuit and the timing circuit are to detect the previous input group as being the input group that is received immediately prior to receiving the respective input group.

13. The article of manufacture of claim 10 wherein the timing circuit is to define the pixels of each output frame as essentially consisting of the plurality of new and old pixels.

14. The article of manufacture of claim 13 wherein the pixel extraction circuit is to define each output frame so that if the pixels in each row of a frame were numbered 1,2,3, . . . , one half of the odd numbered pixels in each output frame are old pixels and one half are new pixels.

15. The article of manufacture of claim 10 wherein the digital interface is a digital monitor interface.

16. The article of manufacture of claim 10 wherein the digital interface is a main memory interface of a chipset.

17. The article of manufacture of claim 10 wherein the pixel extraction circuit and the timing circuit are to detect that each input group has essentially one-half the number of pixels as an output frame.

18. The article of manufacture of claim 15 further comprising:

a digital to analog converter coupled to the output of the pixel multiplexer to convert the sequence of output frames into analog form.

20. The circuit of claim 19 further comprising:

means for detecting the previous input group as being the input group that is received immediately prior to receiving the respective input group.

21. The circuit of claim 19 further comprising:

means for defining each output frame as essentially consisting of the plurality of new and old pixels.

22. The circuit of claim 21 further comprising:

means for defining each output frame so that if the pixels in each row of a frame were numbered 1,2,3, . . . , one half of the odd numbered pixels in each output frame are old pixels and one half are new pixels.

23. The circuit of claim 19 further comprising:

means for generating a digital sequence which includes the sequence of input groups.

24. The circuit of claim 19 further comprising:

means for detecting that each input group has essentially one-half the number of pixels as an output frame.

25. The circuit of claim 23 further comprising:

means for converting the sequence of output frames into analog form.

19. A circuit comprising:

means for generating a plurality of input pixels for each input group in a sequence of input groups;

means for generating a clock timing signal to display the input pixels;

means for storing the plurality of input pixels for each input group in the sequence; and

means for generating a sequence of output frames, each output frame containing a plurality of output pixels that include (1) a plurality of new pixels which are the input pixels of a respective input group, and (2) a plurality of old pixels which are the input pixels of a previous input group, the previous input group being an input group that is received, by the input pixel generation means, previous to the respective input group.