High speed cross point switch routing circuit with word-synchronous serial back plane

• US 20020075845A1
• Filed: 02/12/2002
• Published: 06/20/2002
• Est. Priority Date: 08/05/1998
• Status: Active Grant

• Current Assignee: Microsemi Communications, Inc. (Microchip Technology Incorporated)
• Original Assignee: Vitesse Semiconductor Sales Corp. (Microchip Technology Incorporated)
• Inventors: Lee, Gary M., Mullaney, John P.
• Granted Patent: US 6,801,518 B2
• Time in Patent Office: Days
• US Class Current: 370/351
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5674 Synchronisation, timing recovery or alignment
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 2012/5684 Characteristics of traffic flows
• CPC Class Codes: H04L 49/1576 Crossbar or matrix
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.

Claims

1. A high speed communication switch circuit comprising:

a plurality of switch ports for transmitting and receiving data;

a switch fabric, the switch fabric providing routes for routing the data among and between the switch ports;

a clock signal generator generating a clock signal defining bit periods for the data;

a timing generator generating a word clock signal defining word cell boundaries for at least some of the data;

an alignment word generator operatively coupled to at least one switch port for generating a switch alignment word for transmission by the at least one switch port;

an alignment word detector operatively coupled to the at least one switch port for detecting a received alignment word received by the at least one switch port.

2. The high speed communication switch circuit of claim 1 wherein the switch ports comprise receive switch ports for receiving data and transmit switch ports for transmitting data.

3. The high speed communication switch circuit of claim 2 further comprising plurality of alignment word detectors, each alignment word detector operatively coupled to a corresponding receive switch port.

4. The high speed communication switch circuit of claim 3 further comprising a plurality of data recovery units operatively coupled to a corresponding receive switch port for recovering data received by the receive switch port.

5. The high speed communication switch circuit of claim 4 further comprising an arbitration circuit for configuring the switch fabric and port logic circuitry associated with each receive switch port for routing connection requests to the arbitration circuit.

6. The high speed communication switch circuit of claim 5 wherein the data comprises payload and overhead bits.

7. The high speed communication switch circuit of claim 6 further comprising routing means for routing the overhead bits received by a receive switch port to a transmit switch port, and wherein the port logic circuitry includes means for detecting the overhead bits received by the receive switch port and means for providing the routing means the overhead bits.

8. A method of synchronizing clock signals of transceivers and switches in a high speed data communication switching system comprising:

providing a reference clock signal from a clock signal generator;

forming a word cell boundary signal using the reference clock signal;

transmitting a predefined transmit data word to a receiver, the data words having bit periods defined by the reference clock signal and word cell boundaries defined by the word cell boundary signal;

receiving a receive data word from a receiver; and

determining if the receive data word matches a predefined data word.

9. The method of synchronizing clock signals of transceivers and switches in a high speed data communication switching system of claim 8 further comprising continuing to transmit the predefined data word to the receiver until receiving a receive data word from the receiver which matches the predefined data word.

10. The method of synchronizing clock signals of transceivers and switches in a high speed data communication switching system of claim 9 further comprising transmitting an idle word when the receive data word matches the predefined data word.

11. A method of synchronizing clock signals of transceivers and switches in a high speed data communication switching system comprising:

transmitting a reset request signal;

receiving a signal containing repetitions of a first predefined alignment word;

extracting a clock signal from the signal containing repetitions of the first predefined alignment word;

generating a receive word cell boundary clock signal based on the clock signal;

extracting a test alignment word from the signal containing repetitions of the first predefined alignment word using the clock signal and the receive word cell boundary clock signal; and

determining if the test alignment word matches the first predefined alignment word.

12. The method of synchronizing clock signals of transceivers and switches in a high speed data communication switching system of claim 11 further comprising shifting the word cell boundary clock signal by a predefined period of the clock signal if the test alignment word does not match the predefined alignment word.

13. The method of synchronizing clock signals of transceivers and switches in a high speed data communication switching system of claim 12 further comprising:

generating a transmit word cell boundary based on the clock signal;

transmitting a second predefined alignment word using the transmit word cell boundary;

determining if a predefined idle word has been received after a predefined time period subsequent to transmitting the second predefined alignment word; and

shifting the transmit word cell boundary by a predefined period of the clock signal if no predefined idle word has been received after the predefined time period subsequent to transmitting the second predefined alignment word.

14. The method of synchronizing clock signals of transceivers and switches in a high speed data communication switching system of claim 13 wherein the predefined period of the clock signal is one period.

15. The method of synchronizing clock signals of transceivers and switches in a high speed data communication switching system of claim 14 wherein the first predefined alignment word and the second predefined alignment word are comprised of like bit patterns.

17. The frequency locked switch and transceiver system of claim 16 wherein the switch further comprises a plurality of alignment word generators operatively coupled to corresponding ones of the plurality of switch transmit ports for generating alignment words for transmission to corresponding ones of the plurality of transceivers and wherein the plurality of transceivers further comprise an alignment word detector operatively coupled to the serial input port for detecting alignment words received from the switch.

18. The frequency locked switch and transceiver system of claim 17 wherein the switch further comprises a plurality of data recovery units operatively coupled to corresponding serial switch receive ports for adjusting the bit period defined by the switch clock signal for data received by the serial switch receive ports.

19. The frequency locked switch and transceiver system of claim 18 wherein the plurality of transceivers further comprise a receive word timing generator operatively coupled to the clock recovery unit and the alignment word detector for defining word cell boundaries of serial data received from the switch.

20. The frequency locked switch and transceiver system of claim 19 wherein the plurality of transceivers further comprise a bit shifter operatively coupled to the alignment word detector and receive word timing generator for commanding a change in the word cell boundaries defined by the receive word timing generator.

21. The frequency locked switch and transceiver system of claim 20 wherein the plurality of transceivers further comprise a transmit word timing generator operatively coupled to the clock recovery unit and the alignment word detector for defining word cell boundaries of serial data transmitted to the switch.

22. The frequency locked switch and transceiver system of claim 21 wherein the plurality of transceivers further comprise a transmit input buffer for storing data for transmission to the switch and a receive output buffer for storing data received from the switch, with data clocked out of the transmit input buffer and into the receive output buffer on word cell boundaries defined by the transmit timing generator.

23. The frequency locked switch and transceiver system of claim 22 wherein the switch further comprises an arbitration circuit for reconfiguring the switch fabric in response to data received by a one of the switch receive ports from a one of the transceivers.

25. The high speed communications transceiver circuit of claim 24 further comprising an alignment word detector for comparing a contiguous number of bits received by the serial input port with a predefined bit pattern.

26. The high speed communications transceiver circuit of claim 25 further comprising a receive word timing generator operatively coupled to the alignment word detector and the clock recovery unit for defining a receive word cell boundary for contiguous bits received by the serial input port.

27. The high speed communications transceiver circuit of claim 26 further comprising a transmit word timing generator operatively coupled to the alignment word detector and the clock recovery unit for defining a transmit word cell boundary for contiguous bits transmitted by the serial output port.

16. A frequency locked switch and transceiver system comprising:

a switch comprising;

a plurality of serial switch transmit and receive ports;

a switch fabric serially reconfigurably interconnecting the serial switch transmit and receive ports; and

a clock signal generator generating a switch clock signal defining a bit period for data transmitted and received by the serial switch transmit and receive ports; and

a plurality of transceivers connected to the serial switch ports, each transceiver comprising;

a serial input port and a serial output port, the serial input port connected to a one of the serial switch transmit ports and the serial output port connected to a one of the serial switch receive ports;

a clock recovery unit operatively coupled to the serial input port;

a demultiplexer operatively coupled to the serial input port and the clock recovery unit; and

a multiplexor operatively coupled to the serial output port and the clock recovery unit.

24. A high speed communication transceiver circuit comprising:

a serial input port and a serial output port, the serial input port connected to a one of the serial switch transmit ports and the serial output port connected to a one of the serial switch receive ports;

a clock recovery unit operatively coupled to the serial input port;

a demultiplexer operatively coupled to the serial input port and the clock recovery unit; and

a multiplexor operatively coupled to the serial output port and the clock recovery unfit.

28. A switching system comprising:

a switch circuit including a plurality of switch ports transmitting and receiving data, a switch fabric coupled to the plurality of switch ports, the switch fabric providing transmission channels for routing data among and between the switch ports, and a timing reference signal defining bit and word cell boundaries for the data transmitted by each switch port; and

a plurality of transceiver circuits linked to a corresponding one of the plurality of switch ports, the transceiver circuits receiving data from and transmitting data to the switch ports, each transceiver circuit comprising;

means for recovering a timing signal from data received from the switch port, the timing signal representing bit cell boundaries of the data as defined by the switch circuit;

means for recovering word cell boundaries from a data received from the switch port, such that each transceiver circuit'"'"'s word cell boundaries correspond to the switch circuit word cell boundaries defined by the timing reference signal; and

means for transmitting data to the switch port, the timing signal defining bit and word cell boundaries for the data transmitted by the transceiver circuit.

29. A high speed self-routing network switching system in which internal timing reference signals of a plurality of transceiver circuits are word synchronized to a master word clock timing reference signal developed by a switch circuit, the switch circuit including a plurality of switch ports each coupled to communicate with a corresponding transceiver circuit, and a switch fabric for routing data among and between the switch ports, the system comprising:

a first alignment word generator circuit disposed in the switch, the first alignment word generator defining alignment words for transmission to a transceiver, each alignment word generated in accord with word boundaries defined by the master word clock timing reference;

an alignment word detector, disposed in each transceiver, the alignment word detector adjusting a receive word clock boundary until the alignment word detector detects proper alignment, the alignment word detector thereby defining a local word clock timing signal; and

a second alignment word generator circuit, disposed in each transceiver circuit, the second alignment word generator defining alignment words for transmission to the switch in accord with word boundaries defined by the local word clock timing signal, the switch detecting alignment words received from a transceiver with the master word clock timing reference.

30. In a high speed network switching system in which internal timing reference signals of a plurality of transceiver circuits are frequency locked to a timing reference signal developed by a switch circuit, the switch circuit including a plurality of switch ports each coupled to communicate with a corresponding transceiver circuit, and a switch fabric for routing data among and between the switch ports, a method for word synchronizing a transceiver to a master word clock timing reference, the method comprising:

generating alignment words in the switch for transmission to a transceiver, each alignment word generated in accord with word boundaries defined by the master word clock timing reference;

receiving alignment words by an alignment word detector disposed in a transceiver;

adjusting a receive word clock boundary until the alignment word detector detects proper alignment of the alignment words; and

defining a receive word clock timing signal when the alignment word detector detects proper alignment of the alignment words;

31. The method of claim further comprising:

defining alignment words in the transceiver for transmission to the switch in accord with word boundaries defined by a transmit word clock timing signal;

detecting alignment words received from a transceiver by the switch with the master word clock timing reference; and

re-transmitting alignment words to the transceiver if the received alignment word is not properly aligned within the master word clock word boundaries, the transceiver iteratively bit shifting the transmit word clock timing signal until the switch determines the received alignment word is properly aligned within the master word clock word boundaries.

32. A high speed network switching apparatus, comprising a switch circuit, including a plurality of switch ports, each switch port defining a transmission channel and adapted to transmit and receive a high-speed serial data stream, switch fabric coupled to the plurality of switch ports, the switch fabric routing data among and between the switch ports, and a plurality of transceiver circuits, each transceiver circuit configured to transmit and receive a high speed serial data stream between a corresponding one of the plurality of switch ports so as to establish a transmission channel between a corresponding transmitting transceiver circuit and a corresponding receiving transmitter circuit, the data stream including command and data words further comprising:

a data portion; and

a header portion, wherein the header portion includes overhead bits configured to provide a ready-to-receive indication from a receiving transceiver to a transmitting transceiver circuit when the overhead bits are in a first binary sequence, a not-ready-to-receive indication from a receiving transceiver to a transmitting transceiver when the overhead bits are in a second binary sequence, the switch adaptively routing the overhead bits from the corresponding receiving transceiver circuit to the corresponding transmitting receiver circuit.

33. A high speed network switching system, comprising:

a switch circuit, including a plurality of transmission channels, the switch circuit further including;

a plurality of switch ports, each switch port defining a transmission channel and adapted to transmit and receive a high-speed serial data stream;

a switch fabric coupled to the plurality of switch ports, the switch fabric routing data among and between the switch ports;

a plurality of transceiver circuits, each transceiver configured to transmit and receive a high speed serial data stream between a corresponding one of the plurality of switch ports so as to establish a transmission channel between the switch fabric and external user application circuitry, each transceiver circuit including;

a transmit data buffer coupled to the transceiver over a parallel interface, the interface defining at least an enable signal for enabling parallel data to be read to the transceiver when the signal is in a first state, and for disabling parallel data from being read to the transceiver when the signal is in a second state;

a receive data buffer coupled to the transceiver over a parallel interface, the interface defining at least an indication signal when the data buffer is almost full;

means for appending an overhead bit field to a data or command word, the overhead bit field containing overhead bits having a first configuration when the almost full indication signal is asserted, the overhead bits having a second configuration when the almost full indication signal is not asserted;

means for reading an appended overhead bit field, the means for reading asserting the read enable signal to the first, enable, state when the overhead bits are in the second configuration, and asserting the read enable signal to the second, disable, state when the overhead bits are in the first configuration.

36. The high speed network switching system of claim 35 wherein the overhead bits transmitted by a particular transceiver indicate that the particular transceiver is able to receive data when the overhead bits are configured in a first pattern.

37. The high speed network switching system of claim 35 wherein the overhead bits transmitted by a particular switch transmit port to a particular transceiver indicate acknowledgment of receipt by the particular switch receive port of a request by the particular transceiver.

38. The high speed network switching system of claim 35 wherein the overhead bits transmitted by a particular switch transmit port to a particular transceiver indicate the granting of a connection request requested by the particular transceiver.

34. A data switching system comprising:

a switch having a plurality of ports receiving and transmitting data, a plurality of a data paths for routing the data from a port to another port, and means for selecting a one of the data paths for routing the data from the port to the other port;

a plurality of transceivers, each of the transmitters transmitting data to and receiving data from a one of the plurality of ports over at least one transmission line;

the switch further comprising a word generator generating an alignment word for transmission to a transceiver upon selection of a one of the data paths for routing the data from the port to the other port and a comparator for comparing a transceiver word received from the transceiver to the alignment word; and

the transceiver further comprising a bit pattern generator for generating a bit pattern forming the transceiver word in response to receipt of the alignment word, the bit pattern being based on the alignment word.

35. A high speed network switching system comprising a switch including a plurality of pairs of switch transmit and receive ports, each of the pairs of switch transmit and receive ports coupled to a corresponding one of a plurality of transceivers, the transceivers adapted to transmit serial data formed in data words, the data words comprising overhead bits and payload, to the switch receive ports and to receive serial data formed in data words from the switch transmit ports, the switch including:

a switch fabric reconfigurably interconnecting the switch transmit and receive ports such that the switch fabric provides a switch transmit port of a first pair of switch transmit and receive ports with payload from a switch receive port of a second pair of switch transmit and receive ports and the switch fabric provides the switch transmit port of a third pair of switch transmit and receive ports with payload from switch receive port of the first pair of switch transmit and receive ports;

a reverse switch fabric reconfigurably interconnecting the switch transmit and receive ports such that the switch fabric provides the switch transmit port of the first pair of switch transmit and receive ports with overhead bits from the switch receive port of the third pair of switch transmit and receive ports and the switch fabric provides the switch transmit port of the second pair of switch transmit and receive ports with overhead bits from the switch receive port of the first pair of switch transmit and receive ports; and

a means for routing the payload to the switch fabric and means for routing the overhead bits to the reverse switch fabric.