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PLL/DLL dual loop data synchronization

  • US 20020075981A1
  • Filed: 12/20/2001
  • Published: 06/20/2002
  • Est. Priority Date: 12/20/2000
  • Status: Abandoned Application
First Claim
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1. A PLL/DLL dual loop data serializer comprising:

  • a phase lock loop (PLL) including, a phase frequency detector (PFD) receiving a local clock, a voltage controlled oscillator (VCO), a loop filter coupled to said PFD and to said VCO, said loop filter configured to suppress VCO phase noise, and a phase shifter coupled to said VCO and configured in a feedback loop with said PFD;

    a delayed lock loop (DLL) having a digital loop filter coupled to a phase detector and to said phase shifter of said PLL;

    a FIFO register receiving a parallel data input and outputting a signal to said phase detector; and

    a PISO serializer receiving an input from said FIFO and outputting serialized data.

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