Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor

• US 20020076851A1
• Filed: 07/12/2001
• Published: 06/20/2002
• Est. Priority Date: 07/13/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Isothermal Systems Research Inc.
• Inventors: Smetana, Bruce A., Eden, Richard C.
• Granted Patent: US 6,710,441 B2
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/0101 : Neon [Ne]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01037 : Rubidium [Rb]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01043 : Technetium [Tc]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01094 : Plutonium [Pu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H02M 3/33507 : with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H02M 3/33576 : having at least one active switching element at the secondary side of an isolation transformer
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides an integrated circuit assembly including a semiconductive substrate comprising a plurality of field effect transistors having electrically coupled sources and electrically coupled drains comprising regions of the substrate adjacent to a surface of the substrate, and wherein the electrically coupled sources and the electrically coupled drains are collectively configured to conduct power currents in excess of one Ampere; and a package having a plurality of source contacts and a plurality of drain contacts configured to couple with the electrically coupled sources and the electrically coupled drains of the semiconductive substrate, and wherein the source contacts and the drain contacts are provided adjacent to the surface of the package.

Claims

1. An integrated circuit assembly comprising:

a semiconductive substrate comprising a plurality of field effect transistors having electrically coupled sources and electrically coupled drains comprising regions of the substrate adjacent to a surface of the substrate, and wherein the electrically coupled sources and the electrically coupled drains are collectively configured to conduct power currents in excess of one Ampere; and

a package having a plurality of source contacts and a plurality of drain contacts configured to couple with the electrically coupled sources and the electrically coupled drains of the semiconductive substrate, and wherein the source contacts and the drain contacts are provided adjacent to the surface of the package.

2. The assembly of claim 1 wherein the semiconductive substrate further comprises a plurality of source contacts and a plurality of drain contacts coupled with respective ones of the sources and the drains of the field effect transistors, and wherein the source contacts and the drain contacts of the package are configured to couple with respective ones of the source contacts and the drain contracts of the power semiconductor switching device.

3. The assembly of claim 1 further comprising at least one metallization layer coupled with the substrate and configured to couple at least some of the sources in parallel and at least some of the drains in parallel.

4. The assembly of claim 3 wherein the semiconductive substrate further comprises a horizontal interconnect layer formed upon and coupled with the at least one metallization layer, and the horizontal interconnect layer defines a plurality of source contacts and a plurality of drain contacts configured to couple with respective ones of the source contacts and the drain contacts of the package.

5. The assembly of claim 1 wherein the package comprises at least one horizontal interconnect layer to provide the source contacts and the drain contacts.

6. The assembly of claim 1 wherein all electrical connections intermediate the sources and the drains of the substrate and the source contacts and the drain contacts of the package pass through the surface of the substrate.

7. The assembly of claim 1 wherein the package includes one terminal source contact and one terminal drain contact electrically coupled with respective ones of the source contacts and the drain contacts of the package and adapted to electrically couple with devices external of the semiconductor switching device.

8. The assembly of claim 7 wherein the package provides a plurality of electrical paths intermediate the one terminal source contact and the one terminal drain contact and respective ones of the source contacts and the drain contacts of the package, and the electrical paths individually have a resistance less than 1 milliOhm.

9. The assembly of claim 1 wherein the semiconductive substrate comprises a flip chip semiconductive die.

10. The assembly of claim 1 wherein the source contacts and the drain contacts of the power semiconductor device are arranged in alternating columns, and wherein the package comprises a vertical laminate package comprising a plurality of conductive layers corresponding to respective ones of the columns.

11. The assembly of claim 1 wherein the package comprises at least one horizontal interconnect layer.

12. The assembly of claim 11 wherein the at least one horizontal interconnect layer is spaced from the power semiconductor device;

and further comprising a plurality of electrical interconnects intermediate the horizontal interconnect layer and the source contacts and the drain contacts of the power semiconductor device.

13. The assembly of claim 1 wherein the number of source contacts of the power semiconductor device is less than the number of sources and the number of drain contacts of the power semiconductor device is less than the number of drains.

14. The assembly of claim 1 wherein the semiconductive substrate comprises a monolithic substrate including the field effect transistors and auxiliary circuitry.

15. The assembly of claim 1 wherein the semiconductive substrate comprises a monolithic substrate including the field effect transistors and auxiliary circuitry coupled with the plurality of field effect transistors.

16. The assembly of claim 1 wherein the field effect transistors comprise MOSFET devices.

18. The assembly of claim 17 wherein the power transistor comprises a plurality of planar field effect transistors.

19. The assembly of claim 17 wherein the power transistor comprises a plurality of planar field effect transistors coupled in parallel.

20. The assembly of claim 17 further comprising at least one metallization layer coupled with the substrate and configured to couple at least some of the source contacts in parallel and at least some of the drain contacts in parallel.

21. The assembly of claim 20 further comprising a horizontal interconnect layer formed upon and coupled with the at least one metallization layer, and the horizontal interconnect layer defines the source contacts and the drain contacts of the power transistor.

22. The assembly of claim 17 wherein the package comprises at least one horizontal interconnect layer to provide the source contacts and the drain contacts of the package.

23. The assembly of claim 17 wherein all electrical connections intermediate the source contacts and the drain contacts of the substrate and the source contacts and the drain contacts of the package pass through the surface of the substrate.

24. The assembly of claim 17 wherein the power transistor is configured to conduct power currents in excess of one Ampere.

25. The assembly of claim 17 wherein the package includes one terminal source contact and one terminal drain contact electrically coupled with respective ones of the source contacts and the drain contacts of the package and adapted to electrically couple with devices external of the semiconductor switching device.

26. The assembly of claim 25 wherein the package provides a plurality of electrical paths intermediate the one terminal source contact and the one terminal drain contact and respective ones of the source contacts and the drain contacts of the package, and the electrical paths individually have a resistance less than 1 milliOhm.

27. The assembly of claim 17 wherein the semiconductive substrate comprises a flip chip semiconductive die.

28. The assembly of claim 17 wherein the source contacts and the drain contacts of the power semiconductor device are arranged in alternating columns, and wherein the package comprises a vertical laminate package comprising a plurality of conductive layers corresponding to respective ones of the columns.

29. The assembly of claim 17 wherein the package comprises at least one horizontal interconnect layer.

30. The assembly of claim 29 wherein the at least one horizontal interconnect layer is spaced from the power semiconductor device;

and further comprising a plurality of electrical interconnects intermediate the horizontal interconnect layer and the source contacts and the drain contacts of the power semiconductor device.

31. The assembly of claim 17 wherein the number of source contacts of the power semiconductor device is less than the number of sources and the number of drain contacts of the power semiconductor device is less than the number of drains.

32. The assembly of claim 17 wherein the semiconductive substrate comprises a monolithic substrate including the field effect transistors and auxiliary circuitry.

33. The assembly of claim 17 wherein the semiconductive substrate comprises a monolithic substrate including the field effect transistors and auxiliary circuitry coupled with the plurality of field effect transistors.

34. The assembly of claim 17 wherein the power transistor comprises a plurality of MOSFET devices.

36. The method of claim 35 wherein the forming the power transistor comprises forming a plurality of planar field effect transistors.

37. The method of claim 35 wherein the forming the power transistor comprises forming a plurality of planar field effect transistors coupled in parallel.

38. The method of claim 35 further comprising forming at least one metallization layer to couple at least some of the source contacts of the power transistor in parallel and to couple at least some of the drain contacts of the power transistor in parallel.

39. The method of claim 38 wherein the at least one metallization layer forms the source contacts and the drain contacts of the power transistor.

40. The method of claim 38 further comprising forming a horizontal interconnect layer upon the at least one metallization layer to form the source contacts and the drain contacts of the power transistor.

41. The method of claim 35 wherein the providing the package comprises providing at least one horizontal interconnect layer providing the source contacts and the drain contacts of the package.

42. The method of claim 35 wherein the coupling comprises coupling the source contacts and the drain contacts of the power transistor with the source contacts and the drain contacts of the package to pass all electrical signals communicated intermediate the power transistor and the package through the surface of the semiconductive substrate.

43. The method of claim 35 wherein the forming comprises forming the power transistor to conduct power currents in excess of one Ampere.

44. The method of claim 35 wherein the providing the package comprises providing the package having a single source terminal contact and a single drain terminal contact.

45. The method of claim 35 wherein the providing the semiconductive substrate comprises providing a semiconductive die having a flip chip configuration.

46. The method of claim 35 wherein the forming the power transistor comprises forming the power transistor having the source contacts and the drain contacts arranged in alternating columns.

47. The method of claim 46 wherein the providing the package comprises providing the package having the source contacts and the drain contacts arranged in a plurality of conductive layers corresponding to the columns.

48. The method of claim 35 wherein the providing the package comprises providing the package having at least one horizontal layer coupled with the source contacts and the drain contacts of the package.

49. The method of claim 35 wherein the providing the semiconductive substrate comprises providing a monolithic semiconductive substrate, and further comprising forming auxiliary circuitry using the monolithic semiconductive substrate.

50. The method of claim 35 wherein the providing the semiconductive substrate comprises providing a monolithic semiconductive substrate, and further comprising forming auxiliary circuitry coupled with the power transistor.

51. The method of claim 35 wherein the forming comprises forming the power transistor to comprise a plurality of MOSFET devices.

17. An integrated circuit assembly comprising:

a power semiconductor switching device comprising;

a semiconductive substrate having a surface; and

a power transistor formed using the substrate and having a plurality of source contacts and drain contacts adjacent to the surface and configured to conduct power currents; and

a package having a plurality of source contacts and a plurality of drain contacts corresponding to and electrically coupled with respective ones of the source contacts and the drain contacts of the power semiconductor device.

35. A power semiconductor switching device packaging method comprising:

providing a semiconductive substrate having a surface;

forming a power transistor having plurality of source contacts and a plurality of drain contacts using the semiconductive substrate and adjacent to the surface;

providing a package having a plurality of source contacts and a plurality of drain contacts corresponding to the source contacts and drain contacts of the power transistor; and

coupling the source contacts and the drain contacts of the power transistor with the source contacts and the drain contacts of the package.

52. A power semiconductor switching device packaging method comprising:

providing a semiconductive substrate comprising a plurality of planar field effect transistors coupled in parallel and collectively configured to conduct currents in excess of one Ampere;

providing a package having a plurality of source contacts and a plurality of drain contacts; and

coupling the source contacts and the drain contacts with the planar field effect transistors.

53. The method of claim 52 wherein the providing the semiconductive substrate comprises providing the semiconductive substrate comprising the planar field effect transistors having a plurality of source contacts and a plurality of drain contacts configured to couple with respective ones of the source contacts and the drain contacts of the package.

54. The method of claim 52 further comprising forming at least one metallization layer upon the surface of the semiconductive substrate to couple at least some of the planar field effect transistors in parallel.

55. The method of claim 54 wherein the forming comprises forming the at least one metallization layer to define a plurality of source contacts and a plurality of drain contacts configured to couple with respective ones of the source contacts and the drain contacts of the package.

56. The method of claim 54 further comprising forming at least one horizontal interconnect layer upon the at least one metallization layer to form a plurality of source contacts and a plurality of drain contacts to couple with respective ones of the source contacts and the drain contacts of the package.

57. The method of claim 52 wherein the providing the package comprises providing the package including at least one horizontal interconnect layer configured to provide the source contacts and the drain contacts.

58. The method of claim 52 wherein the providing the package comprises providing the package having a single source terminal contact and a single drain terminal contact.

59. The method of claim 52 wherein the coupling comprises coupling the source contacts and the drain contacts of the package with the field effect transistors to pass all electrical signals communicated intermediate the field effect transistors and the package through a surface of the semiconductive substrate.

60. The method of claim 52 wherein the providing the semiconductive substrate comprises providing a semiconductive die having a flip chip configuration.

61. The method of claim 52 wherein the providing the semiconductive substrate comprises providing the semiconductive substrate having a plurality of source contacts and a plurality of drain contacts arranged in alternating columns.

62. The method of claim 61 wherein the providing the package comprises providing the package having the source contacts and the drain contacts arranged in a plurality of conductive layers corresponding to the columns.

63. The method of claim 52 wherein the providing the package comprises providing the package having at least one horizontal layer coupled with the source contacts and the drain contacts of the package.

64. The method of claim 52 wherein the providing the semiconductive substrate comprises providing a monolithic semiconductive substrate having auxiliary circuitry.

65. The method of claim 52 wherein the providing the semiconductive substrate comprises providing a monolithic semiconductive substrate having auxiliary circuitry coupled with the field effect transistors.

66. The method of claim 52 wherein the providing the semiconductive substrate comprises providing the semiconductive substrate comprising the planar field effect transistors implemented as MOSFET devices.