Composite interposer and method for producing a composite interposer

• US 20020076919A1
• Filed: 05/23/2001
• Published: 06/20/2002
• Est. Priority Date: 11/13/1998
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Bernales, Aris, McCormack, Mark Thomas, Peters, Michael G.
• Granted Patent: US 6,521,530 B2
• Time in Patent Office: Days
• US Class Current: 438/637
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0219 : Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/144 : Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/049 : PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/055 : Folded back on itself
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: H05K 3/20 : by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence

Abstract

A composite interposer for providing power and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core formed from a conductive power/ground plane positioned between two dielectric layers. A method for fabricating a composite interposer comprising disposing a silicon layer on a substrate, and selectively etching the silicon layer down to the substrate to develop silicon openings with a silicon profile, and to expose part of the substrate. Vias are formed through the exposed part of the substrate. The method additionally includes filling the vias and the silicon openings with a filler material (e.g., a high-aspect-ratio-capable photodefinable epoxy polymer) to form filled silicon openings and filled vias, forming first openings through the filled silicon openings and through the filled vias, forming second opening through filler material to expose semiconductor devices on the silicon layer, and interconnecting electrically, through the first openings and through the second openings, the exposed semiconductor devices with pads disposed against a bottom of the substrate.

Claims

1. A method for fabricating a composite interposer comprising the steps of:

(a) disposing a silicon layer on a substrate;

(b) selectively etching the silicon layer down to the substrate to develop silicon openings with a silicon profile, and to expose part of the substrate;

(c) forming vias through the exposed part of the substrate;

(d) filling the vias and the silicon openings with a filler material to form filled silicon openings and filled vias;

(e) forming first openings through the filled silicon openings and through the filled vias;

(f) forming second openings through filler material to expose semiconductor devices on the silicon layer; and

(g) interconnecting electrically, through the first openings and through the second openings, the exposed semiconductor devices with pads.

2. The method of claim 1 wherein each of said pads is selected from the group of pads consisting of voltage pads, ground pads, and signal pads.

3. The method of claim 1 wherein said pads are coupled to the bottom of the substrate.

4. The method of claim 1 wherein said selectively etching the silicon layer down to the substrate additionally includes forming a plurality of spaced silicon layers supported by said substrate.

5. The method of claim 2 wherein said selectively etching the silicon layer down to the substrate additionally includes forming a plurality of spaced silicon layers supported by said substrate.

6. The method of claim 4 wherein said forming vias additionally includes forming a plurality of spaced substrates with each spaced substrate supporting a spaced silicon layer.

7. The method of claim 1 additionally comprising filling the first opening with a dielectric filler after said interconnecting electrically.

8. The method of claim 7 additionally comprising filling the first opening with a dielectric filler after said interconnecting electrically.

30. The method of claim 1 additionally comprising testing the semiconductor devices for defectiveness.

34. A composite interposer produced in accordance with the method of claim 1.

9. A method for fabricating a composite interposer comprising the steps of:

(a) disposing a silicon layer on a substrate;

(b) selectively etching the silicon layer down to the substrate to develop silicon openings with a silicon profile, and to expose part of the substrate;

(c) forming vias through the exposed part of the substrate;

(d) filling the vias and the silicon openings with a filler material comprising a photodefinable epoxy polymer having an aspect ratio to form filled silicon openings and filled vias;

(e) forming first openings through the filled silicon openings and through the filled vias;

(f) forming second openings through filler material to expose semiconductor devices on the silicon layer; and

(g) interconnecting electrically, through the first openings and through the second openings, the exposed semiconductor devices with pads.

10. The method of claim 9 wherein each of said pads is selected from the group of pads consisting of voltage pads, ground pads, and signal pads.

11. The method of claim 9 wherein said pads are coupled to the bottom of the substrate.

12. The method of claim 9 wherein said selectively etching the silicon layer down to the substrate additionally includes forming a plurality of spaced silicon layers supported by said substrate.

13. The method of claim 10 wherein said selectively etching the silicon layer down to the substrate additionally includes forming a plurality of spaced silicon layers supported by said substrate.

14. The method of claim 9 additionally comprising filling the first opening with a dielectric filler after said interconnecting electrically.

15. The method of claim 12 additionally comprising filling the first opening with a dielectric filler after said interconnecting electrically.

16. The method of claim 9 wherein said aspect ratio ranges from about 2:

1 to about 40;

1.

17. The method of claim 15 wherein said aspect ratio ranges from about 6:

1 to about 8;

1.

19. The method of claim 18 additionally comprising testing, prior to said selectively removing dielectric material, the silicon layer including the conductive elements to determine if any of the conductive elements are defective.

20. The method of claim 18 wherein said forming a voltage plane includes depositing a metal voltage layer on said dielectric material and coupling same to said exposed conductive elements.

21. The method of claim 20 additionally comprising selectively removing at least one portion of the metal voltage layer to produce a residual voltage layer and to expose metal-filled conductive elements;

and disposing a second dielectric layer over the residual voltage layer and the exposed metal-filled conductive elements.

22. The method of claim 21 wherein said forming a ground plane comprises forming a plurality of vias in said second dielectric layer to produce a residual second dielectric layer and to reexpose the exposed metal-filled conductive elements;

and depositing a metal ground metal on said residual second dielectric layer and in said vias in said second dielectric layer to couple said metal-filled conductive elements to said metal ground metal.

23. The method of claim 22 additionally comprising removing a portion of the metal ground layer to produce exposed second dielectric layer.

24. The method of claim 23 wherein said forming vias includes forming vias through said produced exposed second dielectric layer.

25. The method of claim 24 additionally comprising filling the plated vias.

26. The method of claim 25 additionally comprising capping the filled plated vias.

27. The method of claim 26 wherein said conductive element is a metal pad.

28. The method of claim 18 wherein said conductive element is a semiconductor device.

31. The method of claim 9 additionally comprising testing the semiconductor devices for defectiveness.

32. The method of claim 18 additionally comprising testing the conductive elements for defectiveness.

33. The method of claim 29 additionally comprising testing the conductive elements for defectiveness.

35. A composite interposer produced in accordance with the method of claim 9.

36. A composite interposer produced in accordance with the method of claim 18.

18. A method for fabricating a composite interposer comprising the steps of:

(a) disposing a plurality of conductive elements on a top of a silicon layer, leaving part of a top of the silicon layer exposed;

(b) disposing dielectric material over the conductive elements and the exposed top of the silicon layer;

(c) selectively removing dielectric material from over the conductive elements to expose conductive elements;

(d) forming a voltage plane and a ground plane;

(e) selectively removing silicon from a bottom of the silicon layer to form silicon openings and to expose part of the dielectric material;

(f) filling the silicon openings with a polymer filler, leaving a polymer filler layer on the bottom of the silicon layer;

(g) securing a substrate to the polymer filler layer;

(h) forming vias through the substrate, the polymer filler, and the dielectric material; and

(i) plating the vias.

29. A method for fabricating a composite interposer comprising the steps:

(a) disposing a plurality of conductive elements on top of a silicon layer, leaving part of a top of the silicon layer exposed;

(b) disposing dielectric material over the conductive elements and the exposed top of the silicon layer;

(c) selectively removing silicon from a bottom of the silicon layer to form silicon openings and to expose part of the dielectric material;

(d) filling the silicon openings with a polymer filler, leaving a polymer filler layer on the bottom of the silicon layer;

(e) securing a substrate to the polymer filler layer;

(f) selectively removing dielectric material from over the conductive elements;

(g) forming vias through the substrate, the polymer filler layer, and the dielectric material; and

(h) plating the vias.

37. A composite interposer produced in accordance with the method of claim 29.