Direct phase and frequency demodulation

• US 20020079879A1
• Filed: 12/21/2000
• Published: 06/27/2002
• Est. Priority Date: 12/21/2000
• Status: Active Grant

• Current Assignee: Earl W. Mccune Jr
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: McCune, Earl W. Jr.
• Granted Patent: US 6,969,984 B2
• Time in Patent Office: Days
• US Class Current: 324/76.48
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier
• CPC Class Codes: H04L 27/2337 using digital techniques to measure the time between zero-crossings

Abstract

The present invention, generally speaking, provides a time shift angle demodulator that is of simple construction and has an extended linear range. Range extension is achieved by using the input signals directly, not simply post-processing the S-PFD outputs. In accordance with one embodiment of the invention, a method of measuring the phase or frequency of a periodic input signal uses a periodic reference signal and includes comparing the input signal to the reference signal to obtain a lead signal and a lag signal; changing the count of an up/down counter in dependence on the input signal, the reference signal, the lead signal and the lag signal; and using the lead signal, the lag signal and the count signal to produce a phase or frequency signal. In accordance with another embodiment of the invention, an apparatus for measuring the phase or frequency of a periodic input signal uses a periodic reference signal and includes a comparison circuit for comparing the input signal to the reference signal to obtain a lead signal and a lag signal; a logic circuit, including an up/down counter, responsive to the input signal, the reference signal, the lead signal and the lag signal to change the count of the up/down counter; and circuitry for using the lead signal, the lag signal and the count signal to produce a phase or frequency signal.

Claims

1. A method of measuring the phase or frequency of a periodic input signal using a periodic reference signal, comprising:

comparing the input signal to the reference signal to obtain a lead signal and a lag signal; and

changing the count of an up/down counter in dependence on the input signal, the reference signal, the lead signal and the lag signal; and

using the lead signal, the lag signal and the count signal to produce a phase or frequency signal.

2. The method of claim 1, wherein producing a phase or frequency signal comprises using the lead signal and the lag signal to form a difference signal, and filtering the difference signal to produce an aliased output signal.

3. The method of claim 2, wherein producing a phase or frequency signal further comprises:

adding to the aliased output signal a correction signal representing a positive or negative phase increment to form an unwrapped output signal.

4. The method of claim 3, wherein the correction signal is formed using the count of the up/down counter.

5. Apparatus for measuring the phase or frequency of a periodic input signal using a periodic reference signal, comprising:

a comparison circuit for comparing the input signal to the reference signal to obtain a lead signal and a lag signal;

a logic circuit, including an up/down counter, responsive to the input signal, the reference signal, the lead signal and the lag signal to change the count of the up/down counter; and

means for using the lead signal, the lag signal and the count signal to produce a phase or frequency signal.

6. The apparatus of claim 5, further comprising a pulse combiner/filter responsive to the lead signal and the lag signal to form a difference signal, and a filter for filtering the difference signal to produce an aliased output signal.

7. The apparatus of claim 6, further comprising an adder for adding to the aliased output signal a correction signal representing a positive or negative phase increment to form an unwrapped output signal.

8. The apparatus of claim 7, further comprising circuitry for forming the correction signal using the count of the up/down counter.

9. The apparatus of claim 8, wherein the circuitry for forming the correction signal comprises a multiplier having as one input signal a constant value and having as another input signal the count of the up/down counter.