Gate lines driving circuit and driving method

• US 20020080108A1
• Filed: 05/09/2001
• Published: 06/27/2002
• Est. Priority Date: 12/26/2000
• Status: Active Grant

• Current Assignee: HannStar Display Corporation
• Original Assignee: HannStar Display Corporation
• Inventors: Wang, Chun-Fu
• Granted Patent: US 6,717,566 B2
• Time in Patent Office: Days
• US Class Current: 345/90
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

The present invention provides a driving circuit and the driving method for driving gate control lines G_1 . . . G_N. The gate control lines G_1 . . . G_N are evenly divided into L groups. The driving circuit comprises a gate line control logic circuit, a first level shifter module, a second level shifter module and a multipliexer. The first level shifter module is controlled by the gate line control logic circuit, and scans the driving lines D_1 . . . D_K in each time slot to drive the driving lines one by one, wherein L*K=N. The second level shifter module is controlled by the gate line control logic circuit, and scans the L groups in each time frame to select the L groups one by one. The multiplexer is used to connect the driving lines D_1 . . . D_K to the gate control lines of a selected group, and connect the gate control lines of unselected groups to a predetermined power line.

Claims

1. A driving circuit, for driving gate control lines G_1 . . . G_N for active matrix display, wherein the gate control lines are evenly divided into L groups, comprising:

a gate line control logic circuit;

a first level shifter module, controlled by the gate line control logic circuit, scans the driving lines D_1 . . . D_K in each time slot to drive the driving lines one by one, wherein L*K=N;

a second level shifter module, controlled by the gate line control logic circuit, and scans the L groups in each time frame to select the L groups one by one; and

a multiplexer, for connecting the driving lines D_1 . . . D_K to the gate control lines of a selected group, and connecting the gate control lines of unselected groups to a predetermined power line.

2. The driving circuit as claimed in claim 1, wherein the gate control lines are formed on a display panel.

3. The driving circuit as claimed in claim 1, wherein the multiplexer and the gate control lines are formed on a display panel.

4. The driving circuit as claimed in claim 1, wherein the multiplexer consists of a plurality of active transistors.

5. The driving circuit as claimed in claim 1, wherein the first level shifter module comprises K level shifters.

6. The driving circuit as claimed in claim 1, wherein the second level shifter module comprises 2*L level shifters.

7. The driving circuit as claimed in claim 1, wherein a gate control line G_n has a corresponding transmitting transistor and a corresponding grounded transistor, wherein the drain, source and the gate of the transmitting transistor are respectively coupled to a driving line D_k, the gate control line G_n and a selecting line C_1 from the second level shifter module, and the drain, source and the gate of the grounded transistor are respectively coupled to the gate control line G_n, the predetermined power line, and an inverted selecting line C_1′

, wherein n=(l−

1)*K+k.

8. The driving circuit as claimed in claim 1, wherein L is an integer closest to (N/2)^½

.

9. A driving method of scanning and driving a plurality of gate control lines G_1 . . . G_N, wherein the gate control lines are evenly divided into L groups and scanned one by one in each time frame, the method comprises the following steps:

scanning K driving lines D_1 . . . D_K in a time slot to drive the driving lines one by one, wherein L*K=N; and

scanning the L groups in each time frame to select the L groups one by one and connect the gate control lines of each selected group to the driving lines D_1 . . . D_K.

10. The method of claim 9 further comprises another step:

providing K level shifters to drive D_1 . . . D_K.

11. The driving method of claim 9 further comprises the following step:

forming a multiplexer with a plurality of TFT for connecting the gate control lines of each selected groups to D_1 . . . D_K, and

connecting the gate control lines of unselected groups to a predetermined power line.

12. The driving method of claim 10 further comprises the following step:

providing 2L level shifters to control the multiplexer.

13. The driving method of claim 9 further comprises the following step:

providing a plurality of level shifters to drive D_1 . . . D_K and select the groups.