Host interface for imaging arrays
First Claim
1. An interface for receiving data from an image sensor having an imaging array and a clock generator for transfer to a processor system comprising:
- memory means for storing imaging array data and clocking signals at a rate determined by the clocking signals;
signal generator means for generating a signal for transmission to the processor system in response to the quantity of data in the memory means; and
circuit means for controlling the transfer of the data from the memory means at a rate determined by the processor system.
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Accused Products
Abstract
An interface for receiving data from an image sensor having an imaging array and a clock generator and for transferring the data to a processor system is described. The interface comprises a memory for storing the imaging array data and the clocking signals at a rate determined by the clocking signals. In response to the quantity of data in the memory, a signal generator generates a signal for transmission to the processor system and a circuit controls the transfer of the data from the memory at a rate determined by the processor system. The memory may be a first-in first-out (FIFO) buffer or an addressable memory. The interface is preferably integrated on the same die as the image sensor. The signal generator may generate either an interrupt signal for transmission to the processor system or a bus request signal for transmission to a bus arbitration unit for the processor system.
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Citations
30 Claims
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1. An interface for receiving data from an image sensor having an imaging array and a clock generator for transfer to a processor system comprising:
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memory means for storing imaging array data and clocking signals at a rate determined by the clocking signals;
signal generator means for generating a signal for transmission to the processor system in response to the quantity of data in the memory means; and
circuit means for controlling the transfer of the data from the memory means at a rate determined by the processor system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 25, 26, 29, 30)
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15. An integrated semiconductor imaging circuit for use with an electronic processing system having a data bus comprising:
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an imaging array sensor having an array of sensing pixels and an array address generator integrated on a die; and
interface means integrated on the die for receiving data from the imaging array sensor as determined by the imaging array sensor and adapted to transfer the data to the electronic processing system as determined by the electronic processing system.
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23. An integrated semiconductor imaging circuit for use with an electronic processing system having a data bus comprising:
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an imaging array of sensing pixels;
buffer means for storing data received at an input port and for outputting data through an output port to the data bus;
means for transferring data from a selected pixel to the buffer input port;
means for determining the quantity of data in the buffer means;
means for alerting the electronic processing system when the quantity of data in the buffer means attains a predetermined level; and
means adapted to respond to the electronic processing system for controlling the transfer of the stored data through the buffer means output port.
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24. An integrated semiconductor imaging circuit for use with an electronic processing system having a data bus and a system address/control bus comprising:
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an imaging array of sensing pixels;
buffer means for storing data received at an input port and for outputting data through an output port to the data bus;
means for transferring data from a selected pixel to the buffer input port;
means for determining the quantity of data in the buffer means;
means for seeking control of the data bus when the quantity of data in the buffer means attains a predetermined level; and
means adapted to respond to the availability of the data bus for controlling the transfer of the stored data through the buffer means output port.
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27. An integrated semiconductor imaging circuit for use with an electronic processing system having a data bus comprising:
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an imaging array of sensing pixels;
memory means having a plurality of memory cells arranged in rows and columns for storing data received at an input port and for outputting data through an output port to the data bus;
means for transferring data from a selected pixel to a selected memory cell through the memory means input port;
means for determining the quantity of data in the memory means;
means for alerting the electronic processing system when the quantity of data in the memory means attains a predetermined level; and
means adapted to respond to the electronic processing system for controlling the transfer of the stored data through the memory means output port.
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28. An integrated semiconductor imaging circuit for use with an electronic processing system having a data bus and a system address/control bus comprising:
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an imaging array of sensing pixels;
memory means having a plurality of memory cells arranged in rows and columns for storing data received at an input port and for outputting data through an output port to the data bus;
means for transferring data from a selected pixel to a selected memory cell through the memory input port;
means for determining the quantity of data in the memory means;
means for seeking control of the data bus when the quantity of data in the memory means attains a predetermined level; and
means adapted to respond to the availability of the data bus for controlling the transfer of the stored data through the memory means output port.
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Specification