Packet switching arrangement comprising a cascade control and bufferless cascade switching matrix

• US 20020080795A1
• Filed: 11/16/2001
• Published: 06/27/2002
• Est. Priority Date: 11/18/2000
• Status: Abandoned Application

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Reumermann, Hans-Juergen, Van Wageningen, Andries, Lelkens, Armand
• Application Number:
  US09/996,002
• Publication Number:
  US 20020080795A1
• Time in Patent Office: Days
• US Class Current: 370/395.3
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/13109 Initializing, personal profile
• CPC Class Codes: H04Q 2213/13296 Packet switching, X.25, frame relay
• CPC Class Codes: H04Q 2213/1334 Configuration within the switch
• CPC Class Codes: H04Q 3/68 Grouping or interlacing selector groups or stages

Abstract

The invention relates to a packet switching arrangement comprising a switching network of a plurality of bufferless switching matrices (6) and a plurality of cascade switch controls (7) assigned to one switching matrix (6) each, which switch controls (7) respectively include

an identification analyzer (12) for identifying the input port in a route identification assigned to a packet,

an output allocator (13) for evaluating the route identification,

a configuration unit (14) for storing accepted assignments of a respective input port to an output port,

an identification assignment analyzer (15) for changing and guiding the route identification to a port control (2 to 5).

Claims

1. A packet switching arrangement comprising a switching network which includes a plurality of bufferless switching matrices (6) and a plurality of cascaded switch controls (7) assigned each to a switching matrix (6), which switch controls each include at least

an identification analyzer (12) for identifying the input port in a route identification assigned to a packet,

an output allocator (13) for evaluating the route identification,

a configuration unit (14) for storing accepted assignments of a respective input port and an output port,

an identification assignment analyzer (15) for changing and conveying the route identification to a port controller (2 to 5).

2. A packet switching arrangement as claimed in claim 1, characterized in that the switch control (7) includes a plurality of input allocators (16) for evaluating a plurality of requests sent simultaneously with the route identification.

3. A packet switching arrangement as claimed in claim 2, characterized in that the switch control (7) includes at least a result analyzer (17) for informing the identification analyzer (12) of accepted allocations of various requests sent simultaneously with the route identification and of requests iteratively processed by the switch control (7).

4. A packet switching arrangement as claimed in claim 3, characterized in that each switch control (7) includes a request cascader (18) for comparing and selecting a result locally determined by the output allocator (13) and a result achieved by the preceding switch control (7).

5. A packet switching arrangement as claimed in claim 4, characterized in that each switch control (7) includes an assignment cascader (19) for comparing and selecting a result locally determined by the input allocator (16) and a result achieved by the preceding switch control (7).

6. A packet switching arrangement as claimed in claim 1, characterized in that the switching network is connected to a plurality of input ports via multiplexed signaling links and useful data links.