Inspection analyzing apparatus and semiconductor device

• US 20020081756A1
• Filed: 09/19/2001
• Published: 06/27/2002
• Est. Priority Date: 12/22/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Miyazaki, Yoko, Asahina, Kyoko, Yamana, Kaoru
• Granted Patent: US 6,551,847 B2
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A monitor wafer is processed by a processing apparatus, and thereafter, it is subjected to an inspection in a foreign object inspection apparatus in accordance with an inspection recipe. A measured result obtained by the inspection is compiled and analyzed in a data management system. Generally, a monitor wafer is not assigned a rot name or a wafer name, however, the measured result is assigned an identification name for identifying plural processing apparatuses from one another, and is stored in a database as storage data.

Claims

1. An inspection analyzing method comprising the steps of:

(a) providing one or more monitor wafers for each of a plurality of processing steps individually performed by a plurality of processing apparatuses;

(b) performing an inspection on said one or more monitor wafers to obtain an inspection result; and

(c) assigning said inspection result an identification name for identifying each of said plurality of processing apparatuses having performed said plurality of said processing steps in said step (a) on said one or more monitor wafers subjected to said inspection by which said inspection result is obtained, and storing said inspection result.

2. The inspection analyzing method according to claim 1, further comprising the step of

(d) compiling and analyzing said inspection result stored in said step (c).

3. The inspection analyzing method according to claim 1, wherein

said step (b) includes the step of

(b-1) issuing an alarm when said inspection result falls outside a predetermined allowable range.

4. The inspection analyzing method according to claim 3, further comprising the step of

(e) comparing said inspection result stored in said step (c) for a processing apparatus among said plurality of processing apparatuses in which an alarm has been issued in said step (b-1) with a defect distribution of a product wafer which has undergone said plurality of processing steps executed by said plurality of processing apparatuses.

5. The inspection analyzing method according to claim 1, further comprising the step of

(e) comparing said inspection result stored in said step (c) with a defect distribution of a product wafer which has undergone said plurality of processing steps executed by said plurality of processing apparatuses.

6. The inspection analyzing method according to claim 1, wherein said plurality of processing apparatuses execute the same processing steps.

7. The inspection analyzing method according to claim 1, wherein a plurality of inspection recipes are employed in said step (b) to obtain said inspection result by each of said plurality of inspection recipes.

8. The inspection analyzing method according to claim 1, wherein said step (b) includes the steps of:

(b-1) performing said inspection before and after processes of said plurality of processing steps, respectively; and

(b-2) obtaining, as said inspection result, a difference in said inspection performed before and after said processes of said plurality of processing steps, respectively.

9. The inspection analyzing method according to claim 8, wherein in said step (b-2), said inspection result is obtained as a difference between data on said inspection obtained before said processes and that obtained after said processes, considering position coordinates of said one or more monitor wafers.

10. The inspection analyzing method according to claim 1, wherein in said step (c), said inspection result is provided with a comment indicating the condition of a processing apparatus among said plurality of processing apparatuses that corresponds to said inspection result.

13. The inspection analyzing method according to claim 1, wherein said inspection results stored in said step (c) are converted into a file that corresponds to a browser and transmitted.

15. The inspection analyzing method according to claim 1, wherein said inspection results stored in said step (c) can be delivered on a network.

16. The inspection analyzing method according to claim 1, wherein said inspection results stored in said step (c) can be delivered on a network.

17. A semiconductor device manufactured using a plurality of processing apparatuses to which the inspection analyzing method of claim 1 is applied.

11. An inspection analyzing method, comprising the steps of:

(a) performing a plurality of inspections on a wafer to be processed in a first processing step which is executed by a first processing apparatus;

(b) performing an inspection on a wafer to be processed in said first processing step and a second processing step which is executed after said first processing step; and

(c) comparing a plurality of inspection results obtained by said step (a) with an inspection result obtained by said step (b).

12. The inspection analyzing method according to claim 11, further comprising the step of

(d) compiling and analyzing said inspection results stored in said step (c).

14. The inspection analyzing method according to claim 11, wherein said inspection results stored in said step (c) are converted into a file that corresponds to a browser and transmitted.

18. A semiconductor device manufactured using a plurality of processing apparatuses to which the inspection analyzing method of claim 11 is applied.