METHOD OF MANUFACTURING A DISPLAY UNIT OF A FLAT DISPLAY PANEL HAVING A WIDE VIEWING ANGLE

• US 20020081761A1
• Filed: 05/04/2001
• Published: 06/27/2002
• Est. Priority Date: 12/27/2000
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chen, Chih-Hong, Chen, Chien-Chih, Tai, Ya-Hsiang
• Granted Patent: US 6,432,734 B1
• Time in Patent Office: Days
• US Class Current: 438/30
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

The present invention discloses a method of manufacturing a display unit of a flat display panel having a wide viewing angle. Conventional process, which requires two mask steps for opening contact holes in isolation layers, is improved and merged into only one mask step, whereby the number of masks is reduced from seven to six in fabricating a pixel unit of a FOP LCD panel and the cost of fabrication is also reduced.

Claims

1. A method of manufacturing a displaying unit of a flat display panel having a wide view angle, comprising the steps of:

forming a first conduction layer on a substrate;

patterning and etching the first conduction layer to form a gate layer and a bottom electrode layer on the substrate;

forming a first isolation layer on the substrate;

forming an active layer on the first isolation;

patterning and etching the active layer to form an island-like layer over the gate layer;

forming a second conduction layer over the substrate;

patterning and etching the second conduction layer to form a first and a second source/drain electrodes, a top electrode layer, and a common contact layer;

wherein the first and second source/drain electrodes respectively overlap the two side portions of the island-like layer revealing the island-like layer therebetween, and the bottom electrode layer, the first isolation layer, and the top electrode layer constitute a storage capacitor of the displaying unit of the flat display panel;

forming a second isolation layer over the substrate;

forming a third conduction layer on the second isolation layer;

patterning and etching the third and second isolation layers to form a first contact hole, a second contact hole, a third contact hole, a fourth contact hole, and at least a fifth contact hole;

wherein the first source/drain electrode is revealed in the first contact hole, the common electrode layer is revealed in the second and third contact holes, the top electrode layer is revealed in the fourth contact hole, and the common contact layer is revealed in the fifth contact hole;

forming a fourth conduction layer on the third isolation layer and respectively filling into the first to fifth contact holes; and

patterning and etching the fourth conduction layer to form a plurality of pixel electrodes, a first connecting layer, and a second connecting layer on the third isolation layer;

wherein the first source/drain electrode in the first contact hole and the common electrode layer in the second contact hole are electrically connected via the first connecting layer, the common electrode layer in the third contact hole and the top electrode layer in the fourth contact hole are electrically connected via the second connecting layer, and the pixel electrodes electrically connect to the common contact layer through the fifth contact hole.

2. The method as claimed in claim 1, wherein the first and second conduction layers are metal layers.

3. The method as claimed in claim 1, wherein the third and fourth conduction layers are indium-tin oxide layers.

4. The method as claimed in claim 1, wherein the first and second conduction layers are polysilicon

5. The method as claimed in claim 1, wherein the plural pixel electrodes are formed in the shape of a comb or fingers.