Virtual translation lookaside buffer

• US 20020082824A1
• Filed: 12/27/2000
• Published: 06/27/2002
• Est. Priority Date: 12/27/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Schoenberg, Sebastian, Neiger, Gilbert, Uhlig, Richard, Jeyasingh, Stalinselvaraj, Kagi, Alain, Cota-Robles, Erik, Chou, Stephen, Kozuch, Michael
• Granted Patent: US 6,907,600 B2
• Time in Patent Office: Days
• US Class Current: 704/2
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 9/45537 Provision of facilities of other operating environments, e.g. WINE I/O emulation G06F13/105

Abstract

In one embodiment, a method for supporting address translation in a virtual-machine environment includes creating a guest translation data structure to be used by a guest operating system for address translation operations, creating an active translation data structure based on the guest translation data structure, and periodically modifying the content of the active translation data structure to conform to the content of the guest translations data structure. The content of the active translation data structure is used by a processor to cache address translations in a translation-lookaside buffer (TLB).

Claims

1. A method comprising:

creating a guest translation data structure to be used by a guest operating system for address translation operations;

creating an active translation data structure based on the guest translation data structure; and

periodically modifying content of the active translation data structure to conform to content of the guest translation data structure, the content of the active translation data structure being used by a processor to cache address translations in a translation-lookaside buffer (TLB).

2. The method of claim 1 further comprising emulating functionality of the TLB in response to an address-translation operation performed by the guest operating system.

3. The method of claim 1 further comprising:

receiving control over an event initiated by guest software; and

evaluating the event to identify a cause of the event.

4. The method of claim 3 further comprising determining that the event is caused by an inconsistency between the content of the active translation data structure and the content of the guest translation data structure.

5. The method of claim 4 further comprising modifying one or more entries in the active translation data structure that are associated with the event and do not match corresponding entries in the guest translation data structure.

6. The method of claim 4 further comprising;

comparing the content of the active translation data structure with the content of the guest translation data structure; and

modifying all entries in the active translation data structure that do not match corresponding entries in the guest translation data structure.

7. The method of claim 3 further comprising:

determining that the event is associated with a page fault that would occur under normal operation of the guest software; and

passing control over the event to the guest software.

8. The method of claim 3 further comprising:

determining that the event indicates an attempt of the guest software to manipulate the TLB; and

modifying the content of the active translation data structure.

9. The method of claim 3 further comprising:

determining that the event is associated with a page fault that would not occur under normal operation of the guest software; and

modifying the content of the active translation data structure.

10. The method of claim 1 further comprising initializing the active translation data structure by invalidating every entry in the active translation data structure to emulate the TLB with no entries.

11. The method of claim 1 further comprising maintaining the active translation data structure for each virtual machine running on a computer.

12. The method of claim 1 further comprising maintaining the active translation data structure for each set of privilege levels that can be distinguished by page-based protection.

13. The method of claim 3 further comprising:

determining that the event is caused by an attempt of the guest software to change a privilege level; and

determining whether the changed privilege level may affect page-based protection.

15. The apparatus of claim 14 further comprising the VMM to periodically modify content of the active translation data structure to conform to content of the guest translation data structure and to emulate functionality of the TLB in response to an address translation operation performed by the guest operating system.

16. The apparatus of claim 15 wherein the VMM is to receive control over an event initiated by guest software and to evaluate the event to identify a cause of the event.

17. The apparatus of claim 16 wherein the VMM is to further determine that the event is caused by an inconsistency between the content of the active translation data structure and the content of the guest translation data structure.

18. The apparatus of claim 17 wherein the VMM is to further modify one or more entries in the active translation data structure that are associated with the event and do not match corresponding entries in the guest translation data structure.

19. The apparatus of claim 17 wherein the VMM is to further compare the content of the active translation data structure with the content of the guest translation data structure and to modify all entries in the active translation data structure that do not match corresponding entries in the guest translation data structure.

20. The apparatus of claim 16 wherein the event indicates an attempt of the guest software to manipulate the TLB.

21. The apparatus of claim 16 wherein the event is associated with a page fault generated by a processor in response to an operation performed by the guest software.

22. The apparatus of claim 14 wherein the active translation data structure is maintained for each virtual machine running on a computer.

23. The apparatus of claim 14 wherein the active translation data structure is maintained for each set of privilege levels that can be distinguished by page-based protection.

25. The system of claim 24 wherein the processor is to transfer control over a particular event initiated by guest software to the VMM.

26. The system of claim 24 wherein the memory is to store the active translation data structure for each virtual machine.

27. The system of claim 24 wherein the memory is to store the active translation data structure for each set of privilege levels that can be distinguished by page-based protection.

29. The computer readable medium of claim 28 comprising further instructions causing the processor to perform operations comprising:

receiving control over an event initiated by guest software;

determining that the event is caused by an inconsistency between the content of the active translation data structure and the content of the guest translation data structure; and

modifying one or more entries in the active translation data structure that are associated with the event and do not match corresponding entries in the guest translation data structure.

30. The computer readable medium of claim 28 comprising further instructions causing the processor to perform operations comprising:

receiving control over an event initiated by guest software;

determining that the event is caused by an inconsistency between the content of the active translation data structure and the content of the guest translation data structure;

comparing the content of the active translation data structure with the content of the guest translation data structure; and

modifying all entries in the active translation data structure that do not match corresponding entries in the guest translation data structure.

14. An apparatus comprising:

a guest translation data structure to translate virtual memory addresses into physical memory addresses, the guest translation data structure being managed by a guest operating system;

an active translation data structure to contain data derived from content of the guest translation data structure, the active translation data structure being managed by a virtual machine monitor (VMM); and

a translation-lookaside buffer (TLB) to store address translations derived from the active translation data structure, the TLB being managed by a processor.

24. A system comprising:

a memory to store a guest translation data structure used by a guest operating system for address translation operations and an active translation data structure derived content from content of the guest translation data structure and managed by a virtual machine monitor (VMM); and

a processor, coupled to the memory, to contain a translation-lookaside buffer (TLB), to cache address translations derived from the content of the active translation data structure in the TLB, and to manage the TLB.

28. A computer readable medium that provides instructions, which when executed on a processor, cause said processor to perform operations comprising:

creating a guest translation data structure to be used by a guest operating system for address translation operations;

creating an active translation data structure based on the guest translation data structure; and

periodically modifying content of the active translation data structure to conform to content of the guest translation data structure, the content of the active translation data structure being used by a processor to cache address translations in a translation-lookaside buffer (TLB).