Technique for using shared resources on a multi-threaded processor

• US 20020083252A1
• Filed: 12/27/2000
• Published: 06/27/2002
• Est. Priority Date: 12/27/2000
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Armstrong, William Joseph, Nayar, Naresh, Vossen, Kenneth Charles
• Granted Patent: US 6,785,887 B2
• Time in Patent Office: Days
• US Class Current: 710/260
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A method of handling conflicts between threads, including an initiating thread and at least one other thread, for at least one shared resource in a multi-threaded processing system having a processor and memory includes setting a location in memory for each other thread on the processor with the initiating thread. The initiating thread signals an inter-processor interrupt (IPI) to all other threads on the processor. For each other thread, an interrupt handler is initiated where each other thread: acknowledges receipt of the interrupt, and proceeds to spin on the respective location in memory that was set, thereby guaranteeing that the respective other thread will not be using any shared resource of the processor. The initiating thread waits for other threads on processor to acknowledge the inter-processor interrupt (IPI), and when all the other threads have acknowledged the inter-processor interrupt (IPI), the initiating thread proceeds to save the state of the shared resource in memory, sets the shared resource to the state wanted, uses the shared resource, and restores the original state of the resource. The initiating thread then releases the other threads from their spin by resetting the location in memory that was set above. All the threads then proceed with their computations.

Claims

1. A method of handling conflicts between threads, including an initiating thread and at least one other thread, for at least one shared resource in a multi-threaded processing system having a processor and memory, comprising:

(1) with the initiating thread, setting a location in memory for each other thread on the processor;

(2) with the initiating thread, signaling an inter-processor interrupt (IPI) to all other threads on the processor;

(3) for each other thread, initiating an interrupt handler where each other thread;

(a) acknowledges receipt of the interrupt; and

(b) proceeds to spin on the respective location in memory that was set in step (1), thereby guaranteeing that the respective other thread will not be using any shared resource of the processor;

(4) the initiating thread;

(a) waits for other threads on processor to acknowledge the inter-processor interrupt (IPI); and

(b) when all the other threads have acknowledged the inter-processor interrupt (IPI), the initiating thread proceeds to step (5);

(5) the initiating thread;

(a) saves the state of the shared resource in memory;

(b) sets the shared resource to the state wanted;

(c ) uses the shared resource; and

(d) restores the original state of the resource;

(6) the initiating thread releases the other threads from their spin by resetting the location in memory that was set in step (1); and

(7) all the threads proceed with their computations.

2. The method according to claim 1, wherein the at least one shared resource comprises a special purpose register.

3. The method according to claim 2, wherein the at least one shared resource comprises a non-duplicated, special purpose register.

4. The method according to claim 3, wherein the at least one shared resource comprises a plurality of non-duplicated, special purpose registers.

5. The method according to claim 1, wherein the at least one other thread comprises a plurality of threads.

6. The method according to claim 5, wherein the at least one shared resource comprises a special purpose register.

7. The method according to claim 6, wherein the at least one shared resource comprises a non-duplicated, special purpose register.

8. The method according to claim 7, wherein the at least one shared resource comprises a plurality of non-duplicated, special purpose registers.

9. A computer program product including a recording medium, the recording medium having program instructions stored thereon for implementing the method according to claim 8.

10. A computer program product including a recording medium, the recording medium having program instructions stored thereon for implementing the method according to claim 1.

11. A multi-threaded computer system comprising:

a processor;

at least one shared resource; and

memory for storing a program instructions and data;

wherein the program instructions are executed by the processor to implement the method according to claim 1.

12. The computer system according to claim 11, wherein the at least one shared resource comprises a special purpose register.

13. The computer system according to claim 12, wherein the at least one shared resource comprises a non-duplicated, special purpose register.

14. The computer system according to claim 13, wherein the at least one shared resource comprises a plurality of non-duplicated, special purpose registers.

15. The computer system according to claim 11, wherein the at least one other thread comprises a plurality of threads.

16. The computer system according to claim 15, wherein the at least one shared resource comprises a special purpose register.

17. The computer system according to claim 16, wherein the at least one shared resource comprises a non-duplicated, special purpose register.

18. The computer system according to claim 17, wherein the at least one shared resource comprises a plurality of non-duplicated, special purpose registers.