Method and apparatus for accessing system information

• US 20020083350A1
• Filed: 12/21/2000
• Published: 06/27/2002
• Est. Priority Date: 12/21/2000
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Mirov, Russell N.
• Granted Patent: US 6,782,480 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 12/1433 for a module or a part of a module

Abstract

An option module that may be installed in a computer system is provided. The option module includes functional circuitry that is accessed by the computer system through a conventional connector and/or bus. A nonvolatile memory is also included on the option module and is used to store a variety of system information, such as serial numbers. At least a portion of this system information is protected from alteration by the computer system. A second connector is also provided on the option module. An external device when coupled to the second connector may access all of the system data, and, if desired, alter it. Moreover, the option module need not be installed in the computer system for the external device to access the contents of the memory through the second connector.

Claims

1. A method for accessing information stored in a memory of a device, comprising:

providing power to the memory;

preventing power from being delivered to a select portion of the device; and

accessing data stored in the memory.

2. A method, as set forth in claim 1, wherein accessing data stored in the memory further comprises enabling a write protect terminal of the memory and storing data in preselected locations in the memory.

3. A method, as set forth in claim 2, wherein the device includes a first connector adapted to interface with the select portion and a second connector adapted to interface with the memory, and wherein enabling the write protect terminal of the memory further comprises delivering a signal through the second connector to enable the write protect terminal of the memory.

4. A method, as set forth in claim 1, wherein preventing power from being delivered to the select portion of the device further comprises limiting current flow to the select portion of the device to a preselected level.

5. A method, as set forth in claim 1, wherein the device includes a first connector adapted to interface with the select portion and a second connector adapted to interface with the memory, and wherein providing power to the memory further comprises providing power through the second connector.

6. A method, as set forth in claim 5, wherein accessing data stored in the memory further comprises accessing data stored in the memory through the second connector.

7. A method for operating a device, comprising:

entering a first mode of operation wherein the device receives power and signals over a first connection, the first mode of operation including the device storing system information in a first preselected location in a memory on the device, and the device being prevented from accessing a second preselected location in the memory during the first mode of operation; and

entering a second mode of operation wherein only the memory receives power and signals over a second connection, the second mode of operation including the memory being enabled for access to both the first and second preselected locations through the second connection.

8. An apparatus, comprising:

a memory having a power input terminal and being adapted to operate in a predefined manner in response to receiving current of a preselected magnitude on the power input terminal;

a first voltage source terminal capable of delivering a voltage of a first preselected magnitude;

a resistor coupled between said power input terminal and said first voltage source terminal; and

a second voltage source terminal coupled to the power input terminal and being capable of delivering a current having a magnitude.

9. A device, comprising:

a first connector;

functional circuitry coupled to the first connector and adapted to receive electrical power and signals over the first connector;

a second connector;

a memory coupled to the first and second connectors and adapted to receive electrical power and signals over both the first and second connectors; and

a high impedance device positioned between the functional circuitry and the second connector to prevent substantial current from flowing to the functional circuitry.

10. A device, as set forth in claim 9, wherein the second connector includes an input/output line coupled to the memory wherein data stored in the memory is accessible through the second connector.

11. A device, as set forth in claim 9, wherein the memory includes a write protect terminal that prevents access to all locations within the memory when enabled, and the second connector includes a write protect line coupled to the write protect terminal to permit all locations within the memory to be accessed through the second connector.