DYNAMIC IMPEDANCE MATCHED DRIVER FOR IMPROVED SLEW RATE AND GLITCH TERMINATION

• US 20020084800A1
• Filed: 12/29/2000
• Published: 07/04/2002
• Est. Priority Date: 12/29/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Crittenden, Brent S., Maloney, Timothy J., Volk, Andrew M.
• Granted Patent: US 6,420,899 B1
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: H03K 17/167 using parallel switching arrangements
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

The impedance of a driver driving a load on the other end of a transmission line is dynamically changed to improve slew rate and glitch termination. The driver is controlled to have a low impedance during an initial part of an edge transition, giving the strong drive needed at that time. At a first predetermined position in the edge transition, approximately equal to the flight time, the driver impedance is raised to a value approximately equal to the transmission line impedance to effectively terminate any reflected signals.

Claims

1. A method of dynamically matching the impedance of a driver to improve slew rate and glitch termination for a signal having an edge transition comprising:

a. during an initial part of the edge transition controlling the driver to have a low impedance; and

b. at a first predetermined position in the edge transition, controlling the driver to have a high impedance.

2. The method according to claim 1 wherein the low impedance is an impedance which is less than the impedance of a transmission line to which the driver is coupled and the high impedance is substantially equal to the transmission line impedance.

3. The method according to claim 1 and further including controlling the driver to have the high impedance at the time the edge transition begins and initiating the step of controlling the driver to have a low impedance at a second predetermined position in the edge transition occurring after the beginning of the edge transition but before the second predetermined position.

4. The method according to claim 3 wherein the low impedance is an impedance which is less than the impedance of a line to which the driver is coupled and the high impedance is substantially equal to the transmission line impedance.

5. The method according to claim 2 wherein the driver comprises first and second buffer drivers, with the first buffer driver having the high impedance and the second buffer driver having an impedance which, when placed in parallel with the first buffer driver will provide the low impedance.

6. The method according to claim 5 wherein the steps of controlling the driver to have a low impedance are carried out by enabling both the first and the second buffer drivers and the step of controlling the driver to have high impedance comprises enabling only the first buffer driver.

7. The method according to claim 6 wherein the impedance of the first buffer driver is substantially equal to the transmission line impedance and the impedance of the second buffer driver is substantially equal to one-half that of the first buffer driver.

8. The method according to claim 7 and further including dynamically controlling the impedances of the first and second buffer drivers to maintain their impedances constant.

9. A method according to claim 3 comprising sensing the first predetermined position and the second predetermined position based on time.

10. The method according to claim 9 wherein the controlling the driver to have the high impedance at the time the edge transition begins is done by delaying the occurrence of a data transition to which the edge transition corresponds through logic and controlling the driver to have a low impedance at a second predetermined position in the edge transition occurring after the beginning of the edge transition but before the second predetermined position is done by delaying the data transition through a delay element.

11. A method according to claim 3 comprising sensing the first predetermined position and the second predetermined position based on voltage.

12. The method according to claim 11 wherein the controlling the driver to have the high impedance at the time the edge transition begins is done by delaying a signal responsive to the occurrence of a data transition to which the edge transition corresponds through logic and controlling the driver to have a low impedance at a second predetermined position in the edge transition occurring after the beginning of the edge transition but before the second predetermined position is done by comparing the voltage of the edge transition with a predetermined value.

13. The method according to claim 11 comprising comparing the voltage of the edge transition with a first predetermined value for a falling edge and to a second predetermined voltage for a rising edge.

14. A method according to claim 3 wherein the other end of the transmission line is coupled to a load and the first predetermined position is substantially at position corresponding to a flight time from the driver to the load.

16. The method according to claim 15 wherein the first impedance is substantially matched to the transmission line.

17. The method according to claim 16 and further comprising enabling the second buffer driver at a second predetermined position in the edge transition occurring after the beginning of the edge transition but before the second predetermined position.

19. Apparatus according to claim 18 wherein the first impedance is substantially matched to the transmission line.

20. Apparatus according to claim 18 wherein the buffer enable control is further arranged to enable the second buffer driver at a second predetermined position in the edge transition occurring after the beginning of the edge transition but before the second predetermined position.

21. Apparatus according to claim 18 and further including first and second pre-driver providing inputs to the first and second buffer drivers, the buffer enable control coupled to enable and disable the second pre-driver, to enable and disable its associated buffer driver.

22. Apparatus according to claim 21 and wherein the first and second buffer drivers have a capability for dynamic control of their the impedances and the first and second pre-drivers are coupled to provide inputs to control the impedances of the first and second buffer drivers.

23. Apparatus according to claim 21 wherein the buffer enable control comprises:

a. a first comparator having a negative input coupled to the output of the first and second buffer drivers and a positive input coupled to a first voltage value corresponding a voltage level equal to said first predetermined level required for a rising edge;

b. a second comparator having a positive input coupled to the output of the first and second buffer drivers and a negative input coupled to a second voltage value corresponding a voltage level equal to said first predetermined level required for a falling edge; and

c. a multiplexer having outputs of the first and second gates coupled as inputs, a data line, which is also coupled to inputs of the first and second pre-drivers as a selection input and having an output coupled to an enable input of the second pre-driver.

24. Apparatus according to claim 23 and further including;

a. a first gate, performing an ANDing function having the output of the multiplexer as one input and a driver enable line as a second input and an output coupled to the enable input of the second pre-driver.

25. Apparatus according to claim 21 wherein the buffer enable control comprises;

a. a first gate performing an exclusive OR function having one input coupled to a data line, which is also coupled to inputs of the first and second pre-drivers; and

b. a delay element having an input coupled to the data line and an output coupled to an enable input of the second pre-driver.

26. Apparatus according to claim 25 and further including;

a. a second gate, performing an ANDing function having the output of the exclusive OR gate as one input and a driver enable line as a second input and an output coupled to the enable input of the second pre-driver.

27. Apparatus according to claim 21 wherein the buffer enable control comprises:

a. a first comparator having its negative input coupled to the output of the first and second buffer drivers and its positive input coupled to a first voltage value corresponding to the one of the first and second predetermined levels;

b. a second comparator having its positive input coupled to the output of the first and second buffer drivers and its negative input coupled to a second voltage value corresponding to the other of the first and second predetermined levels;

c. a first gate, performing an ANDing function having outputs of the first and second gates coupled as inputs and having an output coupled to an enable input of the second pre-driver.

28. Apparatus according to claim 27 wherein the first voltage value is approximately ¾

of a voltage supplied to the first and second buffer drivers and the second voltage is approximately ¼

of the voltage supplied to the first and second buffer drivers

29. Apparatus according to claim 28 and further comprising:

a. a second gate performing an exclusive OR function having an output coupled to an input of the first gate and one input coupled to a data line, also coupled as in input to the first and second pre-drivers; and

b. a third comparator having a positive input coupled to the output of the first and second buffer drivers and a negative input coupled to a voltage value corresponding to approximately one-half of the value of a voltage supplied to the first and second buffer drivers, having an output coupled as a third input to the first gate.

30. Apparatus according to claim 21 wherein the buffer enable control comprises:

a. gate performing an exclusive OR function having an output coupled to an enable input of the second pre-driver and one input coupled to a data line that is also coupled as in input to the first and second pre-drivers; and

b. a comparator having a positive input coupled to the output of the first and second buffer drivers and a negative input coupled to a voltage value corresponding to approximately one-half of the value of a voltage supplied to the first and second buffer drivers, and having an output coupled as a second input to the gate.

15. A method of dynamically matching the impedance of a driver to improve slew rate and glitch termination for a signal having an edge transition comprising:

a. enabling a first buffer driver coupled to a transmission line over which the signal is to be sent and having a first impedance prior to an edge transition;

b. during an initial part of the edge transition enabling a second buffer driver, coupled in parallel with the first buffer driver, and having a second impedance; and

c. at a first predetermined position in the edge transition, disabling the second buffer driver.

18. Apparatus to dynamically match the impedance of a driver to improve slew rate and glitch termination for a signal having an edge transition comprising:

a. a first buffer driver to be coupled to a transmission line over which the signal is to be sent and having a first impedance;

b. a second buffer driver coupled in parallel with the first buffer driver having a second impedance; and

c. a buffer enable control to enable both the first and second buffer drivers during an initial portion of an edge transition and to disable the second buffer driver at a first predetermined position in the edge transition.