Phase frequency detector circuit having reduced dead band

• US 20020084815A1
• Filed: 09/04/2001
• Published: 07/04/2002
• Est. Priority Date: 01/03/2001
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Murray, Peter, Murphy, Robert Dale
• Granted Patent: US 6,590,427 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump

Abstract

A digital phase detector that conducts pump up and pump down control signals to a charge pump, wherein each of the control signals has pulses that have a substantially 50/50 duty cycle characteristic when the two input signals, i.e., the input data signal and the feedback clock signal, are substantially in phase. This substantially 50/50 duty cycle output reduces, if not eliminates, inherent problems related to the turn-on delays of the charge pump while maintaining a locked condition. The phase detector may further include an intelligence to detect and handle other situations, such as missing data pulses.

Claims

1. A phase detector for detecting a phase difference between an incoming data signal and a fed-back clock signal, the phase detector comprising:

an edge detector for detecting an edge of the data signal and the fed-back clock signal and producing at least one control signal;

a latch that receives the at least one control signal and latches a plurality of output signals in response to the at least one control signal, wherein the combination of the output signals is indicative of the phase difference between the data signal and the fed-back clock signal.

2. A phase detector as defined in claim 1 wherein the combination of the output signals is an integration function performed by a charge pump.

3. A phase detector as defined in claim 1 wherein a first one of the output signals is high for approximately half a duty cycle plus an amount of time related to the difference in phase between the data signal and the fed-back clock signal, and a second one of the output signals is high for approximately half a duty cycle minus an amount of time related to the difference in phase between the data signal and the fed-back clock signal.

4. A phase detector as defined in claim 3 wherein duty cycles for the output control signals approximates a 50/50 duty cycle when the data signal and the fed-back clock signal are substantially in phase, wherein a 50/50 duty cycle relates to each pulse having a width that is substantially equal to half the time between rising edges of each pulse.

5. A phase detector as defined in claim 4 wherein the phase detector further comprises a missing pulse detector.

6. A phase detector as defined in claim 5 wherein the edge detector comprises a plurality of flip flops and wherein the latch comprises at least two NAND gates configured to form a set/reset latch.

7. A phase detector as defined in claim 5 wherein the missing pulse detector comprises a flip flop and which effectively disables the phase detector when a missing pulse is detected.

8. A phase detector as defined in claim 5 used in combination with a voltage controlled oscillator to generate a phase lock loop system.

9. A method of generating an output clock signal based on an input data signal, the method comprising:

a) detecting a phase difference between the input data signal and a fed-back clock signal;

b) conducting at least two control signals representative of the phase difference to a charge pump, wherein the control comprising digital pulse signals have substantially equal duty cycles when the input data signal and the fed-back clock signal are substantially in phase;

c) generating a voltage signal in response to the at least two control signals; and

d) conducting the voltage signal to a voltage-controlled oscillator, which produces an oscillating output clock signal based on the voltage signal received.

10. A method as defined in claim 9 wherein the act of generating a voltage signal (c) is performed by a charge pump that integrates the at least two control signals, and wherein the voltage signal is minimal when the input data signal and the fed-back clock signal are substantially in phase.

11. A method as defined in claim 10 further comprising:

e) detecting a missing pulse in the data signal; and

f) modifying the at least two control signals in response to detecting the missing pulse to reduce the effect on the charge pump.

12. A method as define in claim 11 wherein the act of modifying the at least two control signals (f) further comprises reversing the values of the at least two control signals upon detecting the missing pulse.

14. A phase lock loop for generating an output clock as defined in claim 13 wherein the system further comprises means for detecting a missing pulse.

15. A phase lock loop system as defined in claim 13 wherein the duty cycles of the control signals are approximate a 50/50 duty cycle when the input data signal and the fed-back clock signal are substantially in phase.

13. A phase lock loop for generating an output clock signal having substantially the same phase as an input data signal, the phase lock loop having a charge pump and a voltage controlled oscillator, the phase lock loop comprising:

a digital phase detector for detecting the phase difference between the input data signal and a fed-back clock signal; and

means for conducting two control signals to the charge pump in response to detecting the phase difference, wherein the two control signals have substantially equal duty cycles when the input data signal and the fed-back clock signal are substantially in phase.