Voltage generating/transferring circuit

• US 20020084834A1
• Filed: 02/27/2002
• Published: 07/04/2002
• Est. Priority Date: 09/08/1999
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakamura, Hiroshi
• Granted Patent: US 6,828,849 B2
• Time in Patent Office: Days
• US Class Current: 327/536
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A plurality of boost units are series-connected. A first MOS transistor is connected between one terminal of the series circuit and a VPP node, and the other terminal of the series circuit is connected to the gate of a second MOS transistor for transferring a boosted voltage. Each boost unit is made up of a third MOS transistor having a gate and drain connected to an input portion and a source connected to an output portion, and a capacitor connected to the input portion. The gate of the first MOS transistor is connected to the input portion of an even-numbered boost unit from the VPP node. This realizes high boosting ability, high voltage transfer capacity, and a low power supply voltage.

Claims

1. A voltage generating/transferring circuit comprising:

a boost unit group including a plurality of boost units series-connected between input and output nodes;

a first transistor connected between the input node and a node for receiving a first voltage; and

a capacitor connected to the output node,

wherein each boost unit has input and output portions, and includes a second transistor having a gate and a drain connected to the input portion and a source connected to the output portion, and a capacitor connected to the input portion, and

a gate of said first transistor is connected to the output node.

2. A voltage generating/transferring circuit according to claim 1, wherein said boost unit group includes not less than three boost units.

3. A voltage generating/transferring circuit according to claim 1, further comprising:

a third transistor which has a gate connected to the output node, and transfers a third voltage,

wherein a second voltage is equal to, or larger than a sum of the third voltage and a threshold voltage of said third transistor.

4. A voltage generating/transferring circuit according to claim 1, wherein a first oscillation signal is input to an even-numbered boost unit from the input node, a second oscillation signal is input to an odd-numbered boost unit from the input node, and the first and second oscillation signals have opposite phases or different timings.

5. A voltage generating/transferring circuit according to claim 1, wherein gate and source voltage levels of said first transistor gradually rise while changing in opposite phases.

6. A voltage generating/transferring circuit according to claim 1, further comprising:

a circuit for fixing the gate of said first transistor to low level in an OFF state.

7. A voltage generating/transferring circuit according to claim 1, wherein a threshold voltage of the second transistor in at least one of the boost units is lower than a threshold voltage of said first transistor.

8. A voltage generating/transferring circuit according to claim 7, wherein a transistor having a threshold voltage lower than the threshold voltage of said first transistor is arranged in a boost unit closest to the output node.

9. A voltage generating/transferring circuit according to claim 1, wherein a threshold voltage of a transistor in a boost unit on the output node side is lower than a threshold voltage of a transistor in a boost unit on the input node side.