Multiple tier array capacitor and methods of fabrication therefor

• US 20020085334A1
• Filed: 12/29/2000
• Published: 07/04/2002
• Est. Priority Date: 12/29/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Brown, Ken, Rodriguez, Jorge Pedro, Figueroa, David G., Chakravorty, Kishore K., Mosley, Larry Eugene, Do, Huong T.
• Granted Patent: US 6,532,143 B2
• Time in Patent Office: Days
• US Class Current: 361/301.4
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/162 incorporating printed capacitors

Abstract

A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material. The capacitors of the various embodiments can be used as discrete devices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricated within the housing.

Claims

1. A capacitor comprising:

a first tier of capacitance, which includes multiple first layers of patterned conductive material separated by layers of dielectric material;

a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers, wherein some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers;

a second tier of capacitance, electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material; and

a second number of second capacitor vias, which extend through the multiple second layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers.

2. The capacitor as claimed in claim 1, wherein the second tier of capacitance is located substantially underneath the first tier of capacitance, and the second capacitor vias extend through the multiple first layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple first layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple first layers.

3. The capacitor as claimed in claim 2, wherein the first number of first capacitor vias is greater than the second number of second capacitor vias.

4. The capacitor as claimed in claim 2, wherein the second capacitor vias extend to a bottom surface of the capacitor so that electrical connections can be made to the second capacitor vias at the bottom surface.

5. The capacitor as claimed in claim 1, further comprising:

at least one additional tier of capacitance, electrically connected between the first tier of capacitance and the second tier of capacitance, which includes multiple additional layers of patterned conductive material; and

additional capacitor vias, which extend through the multiple additional layers, wherein some of the additional capacitor vias make electrical contact with every other one of the multiple additional layers, and others of the additional capacitor vias make electrical contact with a remainder of the multiple additional layers.

6. The capacitor as claimed in claim 1, wherein the capacitor is a discrete device.

7. The capacitor as claimed in claim 6, wherein the first tier of capacitance is located in a center region of the capacitor, and the second tier of capacitance is located in a peripheral region of the capacitor.

8. The capacitor as claimed in claim 1, wherein the capacitor is a ceramic capacitor.

9. The capacitor as claimed in claim 1, wherein the first tier of capacitance and the second tier of capacitance are integrated within a housing.

10. The capacitor as claimed in claim 9, wherein the first tier of capacitance is located in a center region of the housing, and the second tier of capacitance is located in a peripheral region of the housing.

11. A housing comprising:

a first tier of capacitance, which includes multiple first layers of patterned conductive material separated by layers of dielectric material;

a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers, wherein some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers;

a second tier of capacitance, electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material; and

a second number of second capacitor vias, which extend through the multiple second layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers.

12. The housing as claimed in claim 11, wherein the first tier of capacitance is located in a center region of the housing, and the second tier of capacitance is located in a peripheral region of the housing.

13. The housing as claimed in claim 12, wherein the housing is an integrated circuit package, an integrated circuit is mountable over the center region, and the integrated circuit is not mountable over the peripheral region.

14. The housing as claimed in claim 11, wherein the first tier of capacitance and the second tier of capacitance are electrically connected through one or more additional layers of patterned conductive material.

15. The housing as claimed in claim 14, wherein the one or more additional layers of patterned conductive material are located substantially underneath the first tier and the second tier.

16. The housing as claimed in claim 11, further comprising:

at least one additional tier of capacitance, electrically connected between the first tier of capacitance and the second tier of capacitance, which includes multiple additional layers of patterned conductive material; and

additional capacitor vias, which extend through the multiple additional layers, wherein some of the additional capacitor vias make electrical contact with every other one of the multiple additional layers, and others of the additional capacitor vias make electrical contact with a remainder of the multiple additional layers.

17. The housing as claimed in claim 11, wherein the second tier of capacitance is located substantially underneath the first tier of capacitance, and the second capacitor vias extend through the multiple first layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple first layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple first layers.

18. The housing as claimed in claim 17, wherein the first tier, the second tier, the first number of first capacitor vias, and the second number of first capacitor vias are included in a discrete capacitor, which is embedded within the housing.

19. The housing as claimed in claim 17, wherein the first tier, the second tier, the first number of first capacitor vias, and the second number of first capacitor vias are included in a discrete capacitor, which is mounted on the housing.

20. The housing as claimed in claim 17, wherein a first pitch of the first capacitor vias is smaller than a second pitch of the second capacitor vias, providing a pitch conversion for power and ground.

21. The housing as claimed in claim 11, wherein the housing is one of a group comprising an integrated circuit package, an interposer, a socket, and a printed circuit board.

22. The housing as claimed in claim 11, wherein the housing is a ceramic housing.

23. The housing as claimed in claim 11, wherein the housing is an organic housing.

25. The method as claimed in claim 24, wherein fabricating the multi-layer structure comprises fabricating the second tier of capacitance substantially underneath the first tier of capacitance, and wherein forming the second number of second capacitor vias comprises forming the second capacitor vias to extend through the multiple first layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple first layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple first layers.

26. The method as claimed in claim 25, wherein forming the second capacitor vias comprises extending the second capacitor vias to a bottom surface of the capacitor so that electrical connections can be made to the second capacitor vias at the bottom surface.

27. The method as claimed in claim 25, further comprising packaging the multi-layer structure.

28. The method as claimed in claim 24, wherein fabricating the multi-layer structure comprises fabricating the first tier of capacitance in a center region of the capacitor, and fabricating the second tier of capacitance in a peripheral region of the capacitor.

29. The method as claimed in claim 28, wherein fabricating the multi-layer structure comprises fabricating the multi-layer structure as an integrated portion of a housing.

30. The method as claimed in claim 29, wherein fabricating the multi-layer structure as the integrated portion of the housing comprises fabricating the multi-layer structure as an integrated portion of an integrated circuit package, wherein an integrated circuit is mountable over the center region, and the integrated circuit is not mountable over the peripheral region.

24. A method for fabricating a capacitor, the method comprising:

fabricating a multi-layer structure, which includes a first tier of capacitance and a second tier of capacitance electrically connected to the first tier of capacitance, the first tier having multiple first layers of patterned conductive material separated by layers of dielectric material, and the second tier having multiple second layers of patterned conductive material;

forming a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers, wherein some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers; and

forming a second number of second capacitor vias, which extend through the multiple second layers, wherein some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers.