Multiple processor cards accessing common peripherals via transparent and non-transparent bridges

• US 20020085361A1
• Filed: 12/29/2000
• Published: 07/04/2002
• Est. Priority Date: 12/29/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wachel, Robert D.
• Granted Patent: US 6,608,761 B2
• Time in Patent Office: Days
• US Class Current: 361/803
• CPC Class Codes: G06F 1/184 Mounting of motherboards
• CPC Class Codes: G06F 1/185 Mounting of expansion boards
• CPC Class Codes: G06F 1/186 Securing of expansion boards in correspondence to slots provided at the computer enclosure
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438

Abstract

In a Compact PCI system, a method and apparatus for bridging multiple PCI segments in a chassis utilizing backplane connections, instead of a front side component slot. Embodiments of the present invention may be used, with either a transparent or nontransparent bridging system, between multiple PCI segments, to increase the number of shared peripherals in a single Compact PCI chassis.

Claims

1. In a system including a plurality of PCI segments, with each said PCI segment comprising one or more PCI cards mounted in slots on a PCI chassis, a bridge for coupling PCI segments, said bridge comprising:

a board; and

a plurality of connectors mounted on said board for electrically connecting said board to a first and a second PCI segment on a backplane of the PCI chassis.

2. A bridge in accordance with claim 1, wherein:

said plurality of connectors are J1 and J2 connectors.

3. A bridge in accordance with claim 1, wherein:

said board has four connectors for connection to the P1 and P2 groups of pins of said first and second PCI segments.

4. A bridge in accordance with claim 1, further comprising:

a processor mounted on said board and electrically connected to said plurality of connectors, wherein said processor logically connects said first and second PCI segments with a transparent bridge.

5. A bridge in accordance with claim 1, further comprising:

a processor mounted on said board and electrically connected to said plurality of connectors, wherein said processor logically connects said first and second PCI segments with a non-transparent bridge.

6. A bridge in accordance with claim 1, wherein:

said board electrically connects to said first and said second PCI segments in adjacent slots on the PCI chassis.

7. A bridge in accordance with claim 1, wherein:

said board electrically connects to said first and said second PCI segments in non-adjacent slots on the PCI chassis.

8. A bridge in accordance with claim 1, wherein:

said board is configured to mount on said backplane of the PCI chassis in the slot occupied by a transition card.

9. A bridge in accordance with claim 1, wherein:

said plurality of connectors connect only to groups of P1 and P2 pins.

10. In a system including at least three PCI segments, with each PCI segment comprising one or more PCI cards mounted in slots on a PCI chassis, a bridge for connecting to PCI segments, said bridge comprising:

a first board;

a plurality of first board connectors mounted on said first board for electrically connecting said first board to a first and a second PCI segment on the backplane of the PCI chassis;

a second board;

a plurality of second board connectors mounted on said second board for electrically connecting said second board to said second and a third PCI segment on the backplane of the PCI chassis.

11. A bridge in accordance with claim 10, further comprising:

a first processor mounted on said first board and electrically connected to said plurality of first board connectors;

a second processor mounted on said second board and electrically connected to said plurality of second board connectors; and

wherein said first processor and said second processor logically connect said first, said second, and said third PCI segments with a transparent bridge.

12. A bridge in accordance with claim 10, further comprising:

a first processor mounted on said first board and electrically connected to said plurality of first board connectors;

a second processor mounted on said second board and electrically connected to said plurality of second board connectors; and

wherein said first processor and said second processor logically connect said first, said second, and said third PCI segments with a non-transparent bridge.

13. A bridge in accordance with claim 10, wherein:

said first board and said second board are identical; and

said first processor and said second processor are identical.

15. A method in accordance with claim 14, further comprising:

mounting said PCI bridge card in a notch between the PCI chassis and a transition card.

16. A method in accordance with claim 14, further comprising:

connecting a second PCI segment slot and a third PCI segment slot with a second PCI bridge card; and

locating said PCI bridge card along said backplane.

17. A method in accordance with claim 16, wherein:

bridging said first, said second, and said third PCI segments with said first and said second PCI bridge cards is performed with a transparent bridge.

18. A method in accordance with claim 16, wherein:

bridging said first, said second, and said third PCI segments with said first and said second PCI bridge cards is performed with a non-transparent bridge.

20. A method in accordance with claim 19, further comprising:

installing transition cards on the backplane of said pair of adjacent PCI slots substantially perpendicular to the PCI chassis.

14. A method of bridging a plurality of PCI segments mounted on a PCI chassis without occupying a front side slot of said PCI chassis, comprising:

connecting a first PCI segment slot and a second PCI segment slot with a first PCI bridge card; and

locating said PCI bridge card along a backplane.

19. A method of bridging PCI segments on a PCI chassis, comprising:

connecting a pair of adjacent PCI segments with a PCI bridge card across the Groups of P1 and P2 pins on the backplane of a pair of adjacent PCI slots; and

orienting said PCI bridge card substantially parallel to the PCI chassis .