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Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system

  • US 20020087806A1
  • Filed: 01/07/2002
  • Published: 07/04/2002
  • Est. Priority Date: 06/10/2000
  • Status: Active Grant
First Claim
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1. A protocol engine implementing a cache coherence protocol, for use in a multiprocessor computer system, the protocol engine comprising:

  • a signal generator configured to generate a series of clock cycles;

    a memory transaction array configured to store entries representing a plurality of memory transactions, said plurality of memory transactions being associated with the series of clock cycles;

    execution logic configured to execute during a current clock cycle an instruction corresponding to a memory transaction selected in a previous clock cycle, said memory transaction associated with the current clock cycle; and

    scheduling logic configured to select during the current clock cycle an active memory transaction associated with the current clock cycle, if any, from among the plurality of memory transactions represented by said entries in said memory transaction array, said scheduling logic configured to then store during the current clock cycle a first instruction address in an instruction address latch when an instruction corresponding to said first instruction address can be executed during a next clock cycle associated with said current clock cycle, said first instruction address corresponding to the memory transaction selected in the previous clock cycle;

    store during said current clock cycle a second instruction address in said instruction address latch when said instruction corresponding to said first instruction address cannot be executed during said next clock cycle associated with said current clock cycle, said second instruction address corresponding to the active memory transaction; and

    copy during a next clock cycle not associated with the current clock cycle an instruction from an instruction cache into an instruction latch, said instruction corresponding to an instruction address stored in said instruction address latch, the execution logic being further configured to execute during said next clock cycle associated with the current clock cycle an instruction stored in the instruction latch.

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