Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system
First Claim
1. A protocol engine implementing a cache coherence protocol, for use in a multiprocessor computer system, the protocol engine comprising:
- a signal generator configured to generate a series of clock cycles;
a memory transaction array configured to store entries representing a plurality of memory transactions, said plurality of memory transactions being associated with the series of clock cycles;
execution logic configured to execute during a current clock cycle an instruction corresponding to a memory transaction selected in a previous clock cycle, said memory transaction associated with the current clock cycle; and
scheduling logic configured to select during the current clock cycle an active memory transaction associated with the current clock cycle, if any, from among the plurality of memory transactions represented by said entries in said memory transaction array, said scheduling logic configured to then store during the current clock cycle a first instruction address in an instruction address latch when an instruction corresponding to said first instruction address can be executed during a next clock cycle associated with said current clock cycle, said first instruction address corresponding to the memory transaction selected in the previous clock cycle;
store during said current clock cycle a second instruction address in said instruction address latch when said instruction corresponding to said first instruction address cannot be executed during said next clock cycle associated with said current clock cycle, said second instruction address corresponding to the active memory transaction; and
copy during a next clock cycle not associated with the current clock cycle an instruction from an instruction cache into an instruction latch, said instruction corresponding to an instruction address stored in said instruction address latch, the execution logic being further configured to execute during said next clock cycle associated with the current clock cycle an instruction stored in the instruction latch.
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Abstract
The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions. Moreover, the protocol engine is configured to transition from one memory transaction to another in a minimum number of clock cycles. This design improves efficiency for processing commercial workloads, such as on-line transaction processing (OLTP) by taking certain steps in parallel.
27 Citations
60 Claims
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1. A protocol engine implementing a cache coherence protocol, for use in a multiprocessor computer system, the protocol engine comprising:
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a signal generator configured to generate a series of clock cycles;
a memory transaction array configured to store entries representing a plurality of memory transactions, said plurality of memory transactions being associated with the series of clock cycles;
execution logic configured to execute during a current clock cycle an instruction corresponding to a memory transaction selected in a previous clock cycle, said memory transaction associated with the current clock cycle; and
scheduling logic configured to select during the current clock cycle an active memory transaction associated with the current clock cycle, if any, from among the plurality of memory transactions represented by said entries in said memory transaction array, said scheduling logic configured to then store during the current clock cycle a first instruction address in an instruction address latch when an instruction corresponding to said first instruction address can be executed during a next clock cycle associated with said current clock cycle, said first instruction address corresponding to the memory transaction selected in the previous clock cycle;
store during said current clock cycle a second instruction address in said instruction address latch when said instruction corresponding to said first instruction address cannot be executed during said next clock cycle associated with said current clock cycle, said second instruction address corresponding to the active memory transaction; and
copy during a next clock cycle not associated with the current clock cycle an instruction from an instruction cache into an instruction latch, said instruction corresponding to an instruction address stored in said instruction address latch, the execution logic being further configured to execute during said next clock cycle associated with the current clock cycle an instruction stored in the instruction latch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
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49. A protocol engine implementing a cache coherence protocol, for use in a multiprocessor computer system, the protocol engine comprising:
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a signal generator configured to generate a series of clock cycles;
a memory transaction array configured to store entries representing a plurality of memory transactions, said plurality of memory transactions being associated with the series of clock cycles;
a message source, said message source including a plurality of message ports and a plurality of input buffers, said plurality of input buffers configured to store messages received through said plurality of message ports;
execution logic configured to execute during a current clock cycle an instruction corresponding to a memory transaction scheduled in a previous clock cycle, said memory transaction associated with the current clock cycle; and
scheduling logic configured to;
identify a plurality of memory transactions, if any, capable of execution during a next clock cycle associated with the current clock cycle, said plurality of memory transactions including one or more of;
the memory transaction scheduled in a previous clock cycle;
an active memory transaction associated with the current clock cycle stored in the memory transaction array; and
a memory transaction corresponding to a message selected from the message source; and
schedule during the current clock cycle one of the plurality of memory transactions according to a predefined prioritization scheme.
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Specification