Fast suspend to disk

• US 20020087816A1
• Filed: 12/29/2000
• Published: 07/04/2002
• Est. Priority Date: 12/29/2000
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Atkinson, Lee W., Peters, Mark W., Nguyen, Vu T.
• Granted Patent: US 6,546,472 B2
• Time in Patent Office: Days
• US Class Current: 711/156
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system supports a fast hibernation operation to save power, while minimizing the amount of time it takes to enter the hibernation mode, and to resume normal operations. The system periodically stores data from system memory to non-volatile memory, such as a hard disk drive, during normal operations when the system is idle. The system includes activity monitors that detect when the data in memory pages is changed. The system periodically sweeps the monitors, and performs save operations to the non-volatile memory. When the system enters hibernation mode, the system determines which memory pages have been changed since the last save operation, and then saves those pages to memory. As an alternative, the system immediately can enter hibernation by supplying power to the memory pages that have not been saved since the last save operation. To implement this, independent switches under the control of the CPU of memory controller selectively turn off power to unsaved memory pages. The system can also implement a fast resume procedure by restoring the memory pages that have the highest priority, and saving the other pages in the background, or as need by the system devices. Prior to entering the hibernation mode, the pages may be prioritized based on various factors, including the last pages used, the pages used most frequently, or the pages that store the most critical data.

Claims

1. A method of placing a computer system into a low power state, comprising the acts of:

monitoring a page of system memory for write transactions;

setting a designated bit in a register in response to a page of memory receiving a write transaction;

saving a copy into non-volatile memory of one or more pages of system memory that have had the designated bit set in the associated register; and

clearing the designated bit.

2. The method of claim 1, further comprising the acts of:

initiating entry into a hibernation state;

examining the designated bit for each page of memory; and

storing pages of memory to the non-volatile memory that have the designated bit set.

3. The method of claim 2, further comprising the act of setting one or more bits in a control register indicating which pages have been saved in non-volatile memory.

4. The method of claim 3, wherein the non-volatile memory comprises a hard disk drive.

5. The method of claim 3, wherein the one or more bits in the control register are accessed during resume operations to determine which pages have been saved to non-volatile memory.

6. The method of claim 1, wherein the act of saving a copy into non-volatile memory occurs when the system determines that excess processing capacity is available.

7. The method of claim 1, wherein the acts of monitoring and setting are performed by a hardware activity monitor that detects write transactions to a page of memory.

8. The method of claim 1, wherein the low power state is a Hibernation to Disk state where the system memory is not powered.

9. The method of claim 1, further comprising the acts of:

initiating entry into a hibernation state;

examining the designated bit for each page of memory; and

continuing to provide power to pages of memory that have the designated bit set, while discontinuing power to the pages of memory that do not have the designated bit set.

10. The method of claim 9, further comprising the act of restoring data to the pages of memory that do not receive power in the hibernation state.

11. The method of claim 1, further comprising the acts of:

calculating a priority value for each page of memory; and

storing the priority value in a designated register prior to entering the hibernation state.

12. The method of claim 11, wherein the priority value is assigned based on a last used criteria.

13. The method of claim 11, wherein the priority value is assigned based on a most used criteria.

14. The method of claim 11, wherein the priority value is assigned based on a most critical criteria.

15. The method of claim 11, wherein the page with the highest priority is the first page restored after the system resumes from the hibernation state.

17. The method of claim 16, wherein the non-volatile memory comprises a hard drive.

18. The method of claim 16, wherein the flag comprises a dedicated bit in a register, and wherein each page of memory has an associated register.

19. The method of claim 16, wherein the flag comprises a dedicated bit in an activity monitor, and wherein each page of memory has an associated activity monitor.

20. The method of claim 16, wherein the flag comprises a dirty bit in an activity monitor, and wherein the pages of memory are monitored for write transactions by one or more activity monitors.

21. The method of claim 16, wherein the act of saving a copy into non-volatile memory occurs when the system determines that excess processing capacity is available.

16. A method of placing a computer system into a hibernation state, comprising the acts of:

monitoring a page of system memory for write transactions;

setting a flag in response to a page of memory receiving a write transaction;

determining when the computer system has excess processing capacity;

saving a copy in non-volatile memory of at least one page of system memory that has had the flag set;

initiating entry into a hibernation state;

examining the flag for each page of memory; and

storing pages of memory to the non-volatile memory that have the flag set.

22. A method of placing a computer system into a hibernation state, comprising the acts of:

monitoring a page of system memory for write transactions;

setting a flag in response to a page of memory receiving a write transaction;

saving a copy in non-volatile memory of at least one page of system memory that has had the flag set;

initiating entry into a hibernation state;

examining the flag for each page of memory; and

continuing to provide power to pages of that have the flag set, while discontinuing power to the pages of memory that do not have the flag set.

23. The method of claim 22, wherein the flag comprises a dirty bit in an activity monitor, and

wherein the pages of memory are monitored for write transactions by one or more activity monitors.

24. The method of claim 23, wherein the flag comprises a dedicated bit in a register, and wherein each page of memory has an associated register.

25. The method of claim 22, wherein the act of discontinuing power comprises selectively opening a switch that disconnects power to the pages of memory that have been already stored to non-volatile memory.

26. The method of claim 22, wherein the act of saving a copy into non-volatile memory occurs when the system determines that excess processing capacity is available.

28. The method of claim 27, wherein the priority value is assigned based on a last used criteria.

29. The method of claim 27, wherein the priority value is assigned based on a most used criteria.

30. The method of claim 27, wherein the priority value is assigned based on a most critical criteria.

31. The method of claim 27, further comprising the act of passing operation to an operating system prior to restoring pages of memory other than the page with the highest priority value.

32. The method of claim 27, further comprising the act of passing operation to an operating system prior to restoring pages of memory other than the pages with the highest priority values.

27. A method of placing a computer system into a hibernation state, comprising the acts of:

calculating a priority value for each page of system memory;

storing the priority value in a designated register;

storing each page of system memory that includes valid data to non-volatile memory;

entering a hibernation state;

resuming from a hibernation state;

reading the priority value from the designated register; and

restoring the page of system memory with the highest priority before restoring any other page of system memory.

33. A computer system capable of entering a low power mode of operation, comprising:

a CPU;

a system memory that is divided into a plurality of pages;

an activity monitor associated with each page of memory;

a non-volatile memory device;

wherein the CPU periodically copies the data stored in a page of system memory to the non-volatile memory during idle periods in normal system operation, based on write transactions detected by the activity monitor.

34. A system as in claim 33, wherein each activity monitor includes a register with a dedicated dirty bit that indicates if a write transaction has targeted the associated page of memory.

35. A system as in claim 34, wherein the dirty bit is cleared whenever the data for that page is copied to non-volatile memory.

36. A system as in claim 35, wherein the CPU only stored pages that have the dirty bit set when a hibernation mode is initiated.

37. A system as in claim 36, further comprising a plurality of control registers, each of which is associated with a page of memory, and wherein the control registers include a bit indicating if valid data has been stored in non-volatile memory for the associated page of memory.

38. A system as in claim 37, wherein the control registers are saved in non-volatile memory when a hibernation mode is initiated.

39. A system as in claim 38, wherein the non-volatile memory comprises a hard drive.

40. A system as in claim 33, wherein the system memory comprises banks of dynamic random access memory.

41. A system as in claim 33, further comprising a battery that provides power to the computer system, and wherein the frequency with which the CPU copies data to the non-volatile memory varies with the battery charge.

42. A system as in claim 33, wherein the activity monitor includes a register that indicates activity to the associated memory page, and wherein the CPU does not copy a page to non-volatile memory if the activity to a memory page exceeds a threshold amount.

43. A computer system capable of entering a low power mode of operation, comprising:

a CPU;

a system memory that is divided into a plurality of pages;

a plurality of independently controlled switches that selectively couple each page of memory to a power source;

a non-volatile memory device;

a register associated with each page of memory, and wherein each register indicates if valid data has already been stored to non-volatile memory for the associated page;

wherein the CPU opens the switches to the pages of memory that have already had valid data stored to non-volatile data.

44. A system as in claim 43, wherein the CPU also opens the switches to the pages of memory that do not have any valid data.

45. A system as in claim 44, wherein the CPU selectively maintains power to any page of memory that has valid data that has not been saved to non-volatile memory prior to initiation of a hibernation mode.

46. A system as in claim 43, wherein the registers comprise control registers that are saved in non-volatile memory when a hibernation mode is initiated.

47. A system as in claim 44, further comprising an activity monitor that determines if the pages of memory include valid data, and which sets a present bit if that page of memory has valid data.

48. A system as in claim 45, wherein, in response to initiation of the hibernation mode, the CPU stores one or more memory pages to non-volatile memory, and selectively disconnects power to the memory pages that are stored.

50. A system as in claim 49, wherein the CPU passes control to an operating system after restoring the page of memory with the highest priority.

51. A system as in claim 49, wherein the CPU passes control to an operating system after restoring the pages of memory with the highest priorities.

49. A computer system capable of entering a hibernation mode of operation, comprising:

a CPU;

a system memory that is divided into a plurality of pages;

a non-volatile memory device;

a register that includes one or more bits that indicate a priority value assigned to each page of memory;

wherein the CPU stores each page of memory that includes valid data in non-volatile memory when a hibernation mode is initiated, together with the register; and

wherein the CPU restores the page of memory with the highest priority value prior to restoring any other page of memory.