Symmetric multiprocessing (SMP) system with fully-interconnected heterogenous microprocessors
First Claim
1. A data processing system comprising:
- a first processor with a first operational characteristics on a system planar;
interconnection means for later connecting a second, heterogenous processor on said system planar, wherein said interconnection means enables said first processor and said second, heterogenous processor to collectively operate as a symmetric multiprocessor (SMP) system.
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Abstract
Disclosed is a fully-interconnected, heterogenous, multiprocessor data processing system. The data processing system topology has a plurality of processors each having unique characteristics including, for example, different processing speeds (frequency) and different cache topologies (sizes, levels, etc.). Second and third generation heterogenous processors are connected to a specialized set of pins, connected to the system bus. The processors are interconnected and communicate via an enhanced communication protocol and specialized SMP bus topology that supports the heterogeneous topology and enables newer processors to support full downward compatibility to the previous generation processors. Various processor functions are modified to support operations on either of the processors depending on which processor is assigned which operations. The enhanced communication protocol, operating system, and other processor logic enable the heterogenous multiprocessor data processing system to operate as a symmetric multiprocessor system.
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Citations
14 Claims
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1. A data processing system comprising:
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a first processor with a first operational characteristics on a system planar;
interconnection means for later connecting a second, heterogenous processor on said system planar, wherein said interconnection means enables said first processor and said second, heterogenous processor to collectively operate as a symmetric multiprocessor (SMP) system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 14)
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10. A method for upgrading processing capabilities of a data processing system comprising:
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providing a plurality of interrupt pins from a system bus on a system planar to allow later addition of other processors;
enabling direct connection of a new, heterogenous processor to said system planar via said interrupt pins; and
providing support for full backward compatibility by said new, heterogenous processor when said new processor comprises more advanced operational characteristics to enable said data processing system to operate as a symmetric multiprocessor system.
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12. A multiprocessor system comprising:
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a plurality of heterogenous processors with different operational characteristics and physical topology connected on a system planar;
a system bus that supports system centric operations;
interrupt pins coupled to said system bus that provide connection for at least one of said plurality of heterogenous processors;
an enhanced system bus protocol that supports downward compatibility of newer processors that support advanced operational characteristics from among said plurality of processors to processors that do not support said advance operation characteristics.
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Specification