Method and apparatus for reducing components necessary for instruction pointer generation in a simultaneous multithreaded processor

• US 20020087843A1
• Filed: 12/29/2000
• Published: 07/04/2002
• Est. Priority Date: 12/29/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kottapalli, Sailesh
• Granted Patent: US 7,149,880 B2
• Time in Patent Office: Days
• US Class Current: 712/228
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A system and method for a simultaneous multithreaded processor that reduces the number of hardware components necessary as well as the complexity of design over current systems is disclosed. As opposed to requiring individual storage elements for saving instruction pointer information for each re-steer logic component within a processor pipeline, the present invention allows for instruction pointer information of an inactive thread to be stored in a single, ‘inactive thread’ storage element until the thread becomes active again.

Claims

1. A simultaneous multithreaded processor system comprising:

a first multiplexer associated to a first thread of instruction pointers; and

a second multiplexer associated to a second thread of instruction pointers;

said first and second multiplexers to provide instruction pointers for execution in said processor;

first and second storage elements coupled to said respective first and second multiplexers, wherein;

one of the first and second threads is active while the other of said first and second threads is inactive; and

instruction pointers for the active thread are delivered to processor logic and the instruction pointers for the inactive thread are delivered to a storage element for delivery to the processor logic when the inactive thread becomes the active thread.

2. The system of claim 1, further comprising a common multiplexer coupled between said first and second multiplexer and processor logic.

3. The system of claim 2, wherein the common multiplexer receives instruction pointer data sequentially from the first multiplexer and the second multiplexer by utilizing a time-multiplexing protocol.

4. The system of claim 3, wherein the time-multiplexing protocol is a ‘

round-robin’

protocol.

5. The system of claim 1, wherein the first multiplexer and the second multiplexer are priority multiplexers.

6. The system of claim 5, wherein the first multiplexer and the second multiplexer receive instruction pointer information and data from a plurality of stages in a processor pipeline.

7. The system of claim 6, wherein the first multiplexer and the second multiplexer receive instruction pointer information and data from re-steer logic at the plurality of stages in the processor pipeline.

8. The system of claim 7, wherein the first multiplexer and the second multiplexer pass the instruction pointer information and data to the common multiplexer with a pre-determined priority.

9. The system of claim 1, wherein the storage element is a flip-flop device.

10. A method for a simultaneous multithreaded processor system, comprising the steps of:

associating a first multiplexer to a first thread of instruction pointers;

associating a second multiplexer to a second thread of instruction pointers;

providing, by said first and second multiplexers, instruction pointers for execution in said processor;

coupling first and second storage elements to said respective first and second multiplexers;

establishing one of the first and second threads as active and the other of said first and second threads as inactive;

delivering the instruction pointers for the active thread to processor logic; and

delivering the instruction pointers for the inactive thread to a storage element for delivery to the processor logic when the inactive thread becomes the active thread.

11. The method of claim 10, further comprising:

coupling a common multiplexer between said first and second multiplexer and processor logic.

12. The method of claim 11, wherein the common multiplexer receives instruction pointer data sequentially from the first multiplexer and the second multiplexer by utilizing a time-multiplexing protocol.

13. The method of claim 12, wherein the time-multiplexing protocol is a ‘

round-robin’

protocol.

14. The method of claim 10, wherein the first multiplexer and the second multiplexer are priority multiplexers.

15. The method of claim 14, wherein the first multiplexer and the second multiplexer receive instruction pointer information and data from a plurality of stages in a processor pipeline.

16. The method of claim 15, wherein the first multiplexer and the second multiplexer receive instruction pointer information and data from re-steer logic at the plurality of stages in the processor pipeline.

17. The method of claim 16, wherein the first multiplexer and the second multiplexer pass the instruction pointer information and data to the common multiplexer with a pre-determined priority.

18. The method of claim 10, wherein the storage element is a flip-flop device.

20. The system of claim 19, wherein the first multiplexer and the second multiplexer receive instruction pointer information and data from a plurality of stages in a processor pipeline.

21. The system of claim 20, wherein the first multiplexer and the second multiplexer receive instruction pointer information and data from re-steer logic at the plurality of stages in the processor pipeline.

22. The system of claim 19, wherein the first multiplexer and the second multiplexer pass the instruction pointer information and data to the common multiplexer with a predetermined priority.

19. A simultaneous multithreaded processor system comprising:

a first multiplexer associated to a first thread of instruction pointers; and

a second multiplexer associated to a second thread of instruction pointers;

said first and second multiplexers to provide instruction pointers for execution in said processor;

first and second storage elements coupled to said respective first and second multiplexers, wherein;

one of the first and second threads is active while the other of said first and second threads is inactive;

instruction pointers for the active thread are delivered to processor logic and the instruction pointers for the inactive thread are delivered to a storage element for delivery to the processor logic when the inactive thread becomes the active thread; and

a common multiplexer coupled between said first and second multiplexer and processor logic that receives instruction pointer data sequentially from the first multiplexer and the second multiplexer by utilizing a time-multiplexing protocol.