System and method for reducing power consumption in a data processor having a clustered architecture

• US 20020087900A1
• Filed: 12/29/2000
• Published: 07/04/2002
• Est. Priority Date: 12/29/2000
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Homewood, Mark Owen, Jarvis, Anthony X.
• Granted Patent: US 6,772,355 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters, an instruction cache and a power-down controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The power-down controller monitors the instruction cache and each instruction execution pipeline to identify power-down conditions associated with the same and, in response to an identified power-down condition, at least one of: (i) bypasses performance of at least a portion of subsequent ones of the N processing stages associated with an executing instruction, (ii) powers down the instruction cache, and (iii) powers down the data processor.

Claims

1. A data processor having a clustered architecture that comprises an instruction cache and a plurality of clusters, each of said clusters comprising an instruction execution pipeline, each said instruction execution pipeline comprising N processing stages, each of said N processing stages capable of performing at least one of a plurality of execution steps associated with instructions being executed by said clusters, said data processor comprising:

a power-down controller that monitors each said instruction execution pipeline and said instruction cache to identify power-down conditions associated therewith, and that, in response to an identified power-down condition, at least one of;

(i) bypasses performance of at least a portion of subsequent ones of said N processing stages associated with an executing instruction;

(ii) powers down said instruction cache; and

(iii) powers down said data processor.

2. The data processor as set forth in claim 1 further comprising an instruction fetch buffer, and wherein an identified power-down condition indicates detection of at least one of (i) a non-operation in one of said clusters, (ii) a tight-loop condition in said instruction fetch buffer, and (iii) an idle-loop condition.

3. The data processor as set forth in claim 1 wherein said power-down controller, while monitoring each said instruction execution pipeline and said instruction cache, detects a non-operation associated with an instruction executing in an instruction execution pipeline of one of said clusters.

4. The data processor as set forth in claim 3 wherein said power-down controller, in response to detecting said non-operation, bypasses performance of said at least said portion of said subsequent ones of said N processing stages, to thereby reduce power consumption in said subsequent ones of said N processing stages as said executing instruction passes through said instruction execution pipeline.

5. The data processor as set forth in claim 1 further comprising an instruction-fetch buffer.

6. The data processor as set forth in claim 5 wherein said power-down controller powers down said instruction cache in response to identifying a tight-loop condition in said instruction fetch buffer.

7. The data processor as set forth in claim 5 wherein said power-down controller powers down said data processor in response to identifying an idle-loop condition.

8. For use in a data processor having a clustered architecture, said data processor comprising an instruction cache and a plurality of clusters, each of said clusters comprising an instruction execution pipeline, each said instruction execution pipeline comprising N processing stages, each of said N processing stages capable of performing at least one of a plurality of execution steps associated with instructions being executed by said clusters, a method of operating said data processor comprising the steps of:

monitoring each said instruction execution pipeline and said instruction cache to identify power-down conditions associated therewith; and

in response to an identified power-down condition, at least one of (i) bypassing performance of at least a portion of subsequent ones of said N processing stages associated with an executing instruction, (ii) powering down said instruction cache, and (iii) powering down said data processor.

9. The method of operating said data processor as set forth in claim 8 further comprising the step of detecting, while monitoring each said instruction execution pipeline and said instruction cache, a non-operation associated with an instruction executing in an instruction execution pipeline of one of said clusters.

10. The method of operating said data processor as set forth in claim 9 further comprising the step of bypassing, in response to detecting said non-operation, performance of said at least said portion of said subsequent ones of said N processing stages, to go thereby reduce power consumption in said subsequent ones of said N processing stages as said executing instruction passes through said instruction execution pipeline.

11. The method of operating said data processor as set forth in claim 9 wherein said detecting step further comprises detecting that said non-operation is one of a real non-operation and an inserted non-operation during a decode stage of said N processing stages.

12. The method of operating said data processor as set forth in claim 8 wherein said data processor further comprises an instruction fetch buffer and said method further comprises the step of powering down said instruction cache in response to identifying a tight-loop condition in said instruction fetch buffer.

13. The method of operating said data processor as set forth in claim 8 wherein said data processor further comprises an instruction fetch buffer and said method further comprises the step powering down said data processor in response to identifying an idle-loop condition.

15. The processing system as set forth in claim 14 further comprising an instruction fetch buffer, and wherein an identified power-down condition indicates detection of at least one of (i) a non-operation in one of said clusters, (ii) a tight-loop condition in said instruction fetch buffer, and (iii) an idle-loop condition.

16. The processing system as set forth in claim 14 wherein said power-down controller, while monitoring each said instruction execution pipeline and said instruction cache, detects a non-operation associated with an instruction executing in an instruction execution pipeline of one of said clusters.

17. The processing system as set forth in claim 16 wherein said power-down controller, in response to detecting said non-operation, bypasses performance of said at least said portion of said subsequent ones of said N processing stages, to thereby reduce power consumption in said subsequent ones of said N processing stages as said executing instruction passes through said instruction execution pipeline.

18. The processing system as set forth in claim 14 further comprising an instruction-fetch buffer.

19. The processing system as set forth in claim 18 wherein said power-down controller powers down said instruction cache in response to identifying a tight-loop condition in said instruction fetch buffer.

20. The processing system as set forth in claim 18 wherein said power-down controller powers down said data processor in response to identifying an idle-loop condition.

14. A processing system comprising:

a data processor having a clustered architecture;

a memory associated with said data processor;

a plurality of peripheral circuits associated with said data processor for performing selected functions in association with said data processor, wherein said data processor comprises;

an instruction cache;

a plurality of clusters, each of said clusters comprising an instruction execution pipeline of N processing stages, each of said N processing stages capable of performing at least one of a plurality of execution steps associated with instructions being executed by said clusters; and

a power-down controller that monitors each said instruction execution pipeline and said instruction cache to identify power-down conditions associated therewith, and that, in response to an identified power-down condition, at least one of;

(i) bypasses performance of at least a portion of subsequent ones of said N processing stages associated with an executing instruction;

(ii) powers down said instruction cache; and

(iii)powers down said data processor.