CPU power sequence for large multiprocessor systems
First Claim
1. A computer system, comprising:
- a power supply coupled to a control logic, said power supply including a first control signal and Power output lines, wherein said first control signal notifies the control logic when the Power output lines have stabilized;
a plurality of voltage regulator modules (“
VRM”
) coupled to said control logic, wherein each VRM receives a second control signal from the control logic indicating that the Power lines have stabilized; and
a plurality of processors, each of said processors coupled to a VRM, wherein each of said VRMs transmits voltage to a processor to power-on the processor.
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Accused Products
Abstract
A computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The power_good signal notifies the control logic when the Power output lines have stabilized. The computer system also includes a plurality of voltage regulator modules (“VRM”) coupled to the control logic, wherein each VRM receives a power good signal from the control logic. A plurality of processors is also present in the computer system, each of the processors coupled to a VRM. Each of the VRMs transmits voltage to a processor to power-on the processor. Each VRM also transmits to its processor and to the control logic a voltage regulator module power good (“VRMP_G”) signal. The control logic includes means to control the sequential power-on of the processors so as to reduce the current sourcing requirements of the power supply and eliminate power supply surges.
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Citations
28 Claims
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1. A computer system, comprising:
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a power supply coupled to a control logic, said power supply including a first control signal and Power output lines, wherein said first control signal notifies the control logic when the Power output lines have stabilized;
a plurality of voltage regulator modules (“
VRM”
) coupled to said control logic, wherein each VRM receives a second control signal from the control logic indicating that the Power lines have stabilized; and
a plurality of processors, each of said processors coupled to a VRM, wherein each of said VRMs transmits voltage to a processor to power-on the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of powering on processors in a computer system that reduces the current source requirements of the computer system'"'"'s power supply, comprising the steps of:
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a) asserting a first control signal from the power supply after output lines of the power supply have stabilized;
b) placing all processors of the computer system into a reset state; and
c) driving a second control signal to a first voltage regulator module (“
VRM”
). - View Dependent Claims (10, 11, 13, 14, 15, 16, 17, 18, 19)
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12. A computer system, comprising:
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an intelligent power supply including a control logic, said power supply including a plurality of first control signals and Power output lines;
a plurality of voltage regulator modules (“
VRM”
) coupled to said intelligent power supply, wherein each VRM receives a first control signal from the intelligent power supply; and
a plurality of processors, each of said processors coupled to a VRM, wherein each of said VRMs transmits voltage to a processor to power-on the processor.
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20. A computer system, comprising:
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a power supply coupled to a control module, said power supply including a first control signal and Power output lines, wherein said first control signal notifies the control module when the Power output lines have stabilized;
a plurality of voltage regulator modules (“
VRM”
) coupled to said control module, wherein each VRM receives a second control signal from the control module indicating that the Power lines have stabilized; and
a plurality of computer servers organized in racks in a cabinet, each of said computer servers coupled to a VRM, wherein each of said VRMs transmits voltage to a computer server to power-on the computer server. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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Specification