Method for designing large standard-cell based integrated circuits

• US 20020087939A1
• Filed: 05/25/2001
• Published: 07/04/2002
• Est. Priority Date: 09/06/2000
• Status: Abandoned Application

• Current Assignee: Monterey Design Systems, Inc. (Synopsys Incorporated)
• Original Assignee: Monterey Design Systems, Inc. (Synopsys Incorporated)
• Inventors: Reed, David S., Frankle, Jonathan A., Sample, Stephen P., Markosian, Ara, Greidinger, Yaacov I., Lazaryan, Hasmik
• Application Number:
  US09/866,547
• Publication Number:
  US 20020087939A1
• Time in Patent Office: Days
• US Class Current: 716/2
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/3947 global

Abstract

An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.

Claims

1. A method for physically designing an integrated circuit comprising:

importing a netlist description of an integrated circuit design, said netlist description comprising a plurality of hierarchical arranged branches;

selecting atomic blocks for each of said plurality of hierarchically arranged branches, each of said atomic blocks selected to be one or more hierarchy levels above the bottom of a corresponding one of said hierarchically arranged branches, each of said atomic blocks being either an atomic hard block, an atomic soft block or an atomic hierarchical block;

flattening each of said plurality of hierarchically arranged branches by eliminating superfluous levels of hierarchy above said atomic blocks;

partitioning each of said atomic blocks into one of a plurality place and route units (“

PRUs”

); and

positioning said atomic blocks within each of said plurality of PRUs.

2. The method of claim 1 wherein said partitioning step comprises:

determining a physically realizable shape for each of said plurality of PRUs;

determining a physically realizable size for each of said plurality of PRUs; and

determining PRU location for each of said plurality of PRUs.

3. The method of claim 2 wherein said determining PRU shape step comprises:

finding all of said atomic hard blocks and other hard blocks within each of said plurality of PRUs;

calculating an initial PRU shape for each of said plurality of PRUs;

determining whether said atomic hard blocks, said other hard blocks, and all standard cells assigned to said initial PRU shape will fit within said initial PRU shape; and

if said atomic hard blocks, said other hard blocks, and all of said standard cells assigned to said initial PRU shape do not fit within said initial PRU shape, calculating an alternate initial PRU shape and determining whether said atomic hard blocks, said other hard blocks, and all of said standard cells assigned to said initial PRU shape will fit within said initial PRU shape.

4. The method of claim 1 wherein said positioning step further comprises:

moving all of said atomic hard blocks within a particular one of said plurality of PRUs such that each of said atomic hard blocks are one level of hierarchy below said particular one of said PRU;

determining optimal placement of each of said atomic blocks; and

selecting a rectilinear shape for each of said soft atomic blocks and said atomic hierarchical blocks within said particular one of said plurality of PRUs so that said soft atomic blocks and said atomic hierarchical blocks fit within areas of said particular one of said plurality of PRUs left unoccupied by said atomic hard blocks.

5. The method of claim 1 further comprising:

routing interconnections between said plurality of PRUs;

where one of said interconnections crosses an edge of one of said PRUs, assigning a port at said edge of one said plurality of PRUs, said port comprising an electrical contact at said edge of one of said said PRUs;

pushing said interconnections inside said plurality of PRUs; and

creating a physical circuit layout for each of said plurality of PRUs;

6. A method of routing an integrated circuit design comprised of a plurality of place and route units (“

PRUs”

), comprising;

creating dummy ports on each of said PRUs, said dummy ports allowing a net to traverse from a first of said plurality of PRUs to a second of said plurality of PRUs;

connecting said dummy ports on said PRUs by routing nets between them;

determining where said routing nets cross edges of said plurality of PRUs;

deleting said dummy ports; and

generating real ports where said routing nets cross edges of said plurality of PRUs.

7. A method of fitting an integrated circuit design within a predefined area, the integrated circuit design comprising one or more of hard blocks, hierarchical blocks and soft blocks, the hard blocks having a fixed shape, comprising:

determining optimal placement of each of the hard blocks, if any, within the predefined area; and

selecting a rectilinear shape for each of the soft blocks, if any, and hierarchical blocks, if any, so that the soft blocks, if any, and hierarchical blocks, if any, fit within spaces of the predefined area left unoccupied by the hard blocks.