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Method for designing large standard-cell based integrated circuits

  • US 20020087939A1
  • Filed: 05/25/2001
  • Published: 07/04/2002
  • Est. Priority Date: 09/06/2000
  • Status: Abandoned Application
First Claim
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1. A method for physically designing an integrated circuit comprising:

  • importing a netlist description of an integrated circuit design, said netlist description comprising a plurality of hierarchical arranged branches;

    selecting atomic blocks for each of said plurality of hierarchically arranged branches, each of said atomic blocks selected to be one or more hierarchy levels above the bottom of a corresponding one of said hierarchically arranged branches, each of said atomic blocks being either an atomic hard block, an atomic soft block or an atomic hierarchical block;

    flattening each of said plurality of hierarchically arranged branches by eliminating superfluous levels of hierarchy above said atomic blocks;

    partitioning each of said atomic blocks into one of a plurality place and route units (“

    PRUs”

    ); and

    positioning said atomic blocks within each of said plurality of PRUs.

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