Power semiconductor device containing at least one zener diode provided in chip periphery portion

• US 20020088991A1
• Filed: 09/17/2001
• Published: 07/11/2002
• Est. Priority Date: 01/10/2001
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Hisamoto, Yoshiaki
• Granted Patent: US 6,580,121 B2
• Time in Patent Office: Days
• US Class Current: 257/172
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A Zener diode (11) is provided in a chip periphery portion (CPP) which entirely surrounds the periphery of a unit cell portion (UCP) and the periphery of a gate pad portion (GPP) along first to fourth directions (D1) to (D4). The Zener diode (11) has an N⁺-P-N⁺-P-N⁺ structure consisting of an N⁺ type layer (1B), a P type layer (33), an N⁺ type layer (32), a P type layer (31) and an N⁺ type layer (1A), in which these layers extend along the first to fourth directions (D1) to (D4). With this structure, (1) achieving reduction in on-state resistance through enlargement of an effective cell region by downsizing the gate pad and (2) ensuring an improvement in current-voltage characteristic of the Zener diode through an increase in PN junction width, a power semiconductor device having higher electrostatic strength is obtained.

Claims

1. A power semiconductor device comprising:

a semiconductor substrate;

a unit cell portion comprising a plurality of MOS-structure power semiconductor elements formed on a first region which occupies the central part of a main surface of said semiconductor substrate, said unit cell portion comprising a recessed part;

a gate pad portion comprising a wire-bonding-target gate electrode formed over a second region surrounded by said recessed part of said unit cell portion in said main surface of said semiconductor substrate; and

a chip periphery portion comprising at least one Zener diode formed over a third region entirely surrounding the periphery of said unit cell portion in said main surface of said semiconductor substrate.

2. The power semiconductor device according to claim 1,

wherein said chip periphery portion comprises one Zener diode, and

said one Zener diode comprises n semiconductor regions arranged one outside another from the first region located on the side of said periphery of said unit cell portion to the n-th region located on the side of the periphery of said semiconductor substrate, said n semiconductor regions having alternating conductivity types and forming junctions one surrounding another along the periphery of said semiconductor substrate, said n being an odd number of three or larger.

3. The power semiconductor device according to claim 1,

wherein said chip periphery portion comprises,

a plurality of first Zener diodes, and

a plurality of second Zener diodes,

wherein each of said plurality of first Zener diodes comprises n semiconductor regions arranged one outside another from the first semiconductor region having a first conductivity type and located in the center, said n semiconductor regions having alternating conductivity types and forming junctions one surrounding another, said n being an odd number of three or larger,

the n-th semiconductor region in each of said plurality of first Zener diodes having said first conductivity type,

said first semiconductor region in each of said plurality of first Zener diodes being electrically connected, through a first contact hole formed on a surface of said first semiconductor region, to said wire-bonding-target gate electrode in said gate pad portion and to a first gate electrode layer of a corresponding first MOS-structure power semiconductor element provided in said unit cell portion,

said n-th semiconductor region which is the outermost one in each of said plurality of first Zener diodes being electrically connected, through a second contact hole formed on a surface of said n-th semiconductor region, to one main electrode layer of said first MOS-structure power semiconductor element in said unit cell portion,

and wherein each of said plurality of second Zener diodes comprises n semiconductor regions arranged one outside another from the first semiconductor region having said first conductivity type and located in the center, said n semiconductor regions having alternating conductivity types and forming junctions one surrounding another, said n being an odd number of three or larger,

the n-th semiconductor region in each of said plurality of second Zener diodes having said first conductivity type,

said n-th semiconductor region which is the outermost one in each of said plurality of second Zener diodes being electrically connected, through a third contact hole formed on a surface of said n-th semiconductor region, to said wire-bonding-target gate electrode in said gate pad portion and to a second gate electrode layer of a corresponding second MOS-structure power semiconductor element in said unit cell portion,

said first semiconductor region in each of said plurality of second Zener diodes being electrically connected, through a fourth contact hole formed on a surface of said first semiconductor region, to one main electrode layer of said second MOS-structure power semiconductor element in said unit cell portion,

said first gate electrode layer and said second gate electrode layer being electrically connected to each other.

4. The power semiconductor device according to claim 3,

wherein a first sum total of first areas of said first contact holes of said plurality of first Zener diodes and third areas of said third contact holes of said plurality of second Zener diodes is equal to a second sum total of second areas of said second contact holes of said plurality of first Zener diodes and fourth areas of said fourth contact holes of said plurality of second Zener diodes.

5. The power semiconductor device according to claim 4,

wherein said plurality of first Zener diodes and said plurality of second Zener diodes are alternately arranged along said periphery of said semiconductor substrate.

6. The power semiconductor device according to claim 5,

wherein a common gate electrode layer is formed between adjacent ones of said first Zener diodes and said second Zener diodes in said chip periphery portion, said common gate electrode layer being connected to both of said first gate electrode layer and said second gate electrode layer, and

said first semiconductor region of said first Zener diode and said n-th semiconductor region of said second Zener diode are electrically connected to each other through a fifth contact hole formed on a surface of said common gate electrode layer and a gate electrode interconnection filling said fifth contact hole.