SEMICONDUCTOR PACKAGE WITH SHORTENED ELECTRIC SIGNAL PATHS

• US 20020089043A1
• Filed: 12/28/1999
• Published: 07/11/2002
• Est. Priority Date: 12/29/1998
• Status: Abandoned Application

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: PARK, SANG WOOK, HUH, MIN
• Application Number:
  US09/473,004
• Publication Number:
  US 20020089043A1
• Time in Patent Office: Days
• US Class Current: 257/668
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/0101 : Neon [Ne]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01043 : Technetium [Tc]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/206 : Length ranges

Abstract

Disclosed is a semiconductor package and method of fabricating the same. According to the package of the present invention, a semiconductor chip 20 is disposed such that its bonding pad 21 is disposed upwardly. Metal lines 30,31 are deposited along a surface, both sides and a bottom face of the semiconductor chip 20 thereby electrically connecting its upper end 30 to the bonding pad 21 of the semiconductor chip 20. An entire resultant is encapsulated with molding compounds 50,51 such that a lower end of the metal line 31 is exposed thereby forming a ball land. A solder ball 60 is mounted on a portion of the metal line 31 exposed from the molding compound 51.

Claims

1. A semiconductor package comprising:

a semiconductor chip whose bonding pad is disposed upwardly;

a metal line deposited at the bonding pad, both sidewalls and a bottom face of said semiconductor chip;

a molding compound for encapsulating an entire resultant such that a ball land is formed to expose the metal line portion deposited at the bottom face of the semiconductor chip; and

a solder ball mounted on the ball land.

2. The semiconductor package of claim 1, wherein the metal line is divided into an upper metal line deposited at the bonding pad and the both sidewalls of the semiconductor chip, and a lower metal line connected to the upper metal lane and deposited at the bottom face of the semiconductor chip.

3. The semiconductor package of claim 2, wherein an upper insulating layer is sandwiched between the upper metal line and the molding compound, and a lower insulating layer is sandwiched between the lower metal line and the bottom face of the semiconductor chip.

4. The semiconductor package of claim 3, wherein the molding compound is divided into an upper molding compound in the upper portion of the semiconductor chip and a lower molding compound in the lower portion of the semiconductor chip.

5. The semiconductor package of claim 1, wherein the metal line has a multi-layered structure comprising a single layer or over two layers made of a material selected from a group consisting of Al, Cu, Ni, Cr, Ti, Au, Pt, Pd, Pb, Sn.

6. The semiconductor package of claim 1, wherein an under bump metallurgy is formed at the ball land.

7. The semiconductor package of claim 6, wherein the under bump metallurgy is selected from a group consisting of Cu/Ni/Au, Cu/Ni/Au/Cr, Cu/Ni/Au/Co, Cu/Ni/Au/Sn, Cu/Ni/Au/Cr/Sn, Cu/Ni/Au/Co/Sn or Cu/Ni/Pb.

8. The semiconductor package of claim 1, wherein a via hole is formed by etching a selected portion of the molding compound so as to expose the metal line portion deposited on the bonding pad of the semiconductor chip, and the semiconductor package is constructed as a stack type by electrically connecting the metal line portion exposed through the via hole and a solder ball of another package.

9. A semiconductor package comprising:

an upper semiconductor chip whose bonding pad is disposed upwardly;

a lower semiconductor chip disposed at a bottom face of the upper semiconductor chip, wherein the lower semiconductor chip has a bonding pad exposed from the upper semiconductor chip and disposed upwardly;

an upper metal line extended from the bonding pad of the upper semiconductor chip to both sidewalls of the lower semiconductor chip thereby electrically connecting the respective bonding pads of the upper and lower semiconductor chips;

an upper molding compound for encapsulating an entire resultant such that a lower end of the upper metal line and a bottom face of the semiconductor chip are exposed therefrom;

an insulating layer formed at the bottom face of the semiconductor chip;

a lower metal line deposited at the insulating layer, wherein one end of the lower metal line is electrically connected to the lower end of the upper metal line;

a lower molding compound for encapsulating the entire resultant such that a selected portion of the lower metal lines is exposed therefrom;

an under bump metallurgy formed at the portion of the lower metal line exposed from the lower molding compound; and

a solder ball mounted on the under bump metallurgy.

10. A semiconductor package comprising:

an upper semiconductor chip whose bonding pad is disposed upwardly;

a lower semiconductor chip disposed at a bottom face of the upper semiconductor chip, wherein the lower semiconductor chips has a bonding pad exposed from the upper semiconductor chip and disposed upwardly;

an upper metal line deposited at the bonding pad of the lower semiconductor chip and at both sidewalls;

a metal wire for electrically connecting the upper metal line and the bonding pad of the upper semiconductor chip;

an upper molding compound for encapsulating an entire resultant such that a lower end of the upper metal line and a bottom face of the semiconductor chip are exposed therefrom;

an insulating layer formed at the bottom face of the semiconductor chip;

a lower metal line deposited at the insulating layer, wherein one end of the lower metal line is electrically connected to the lower end of the upper metal line;

a lower molding compound for encapsulating the entire resultant such that a selected portion of the lower metal lines is exposed therefrom;

an under bump metallurgy formed at the portion of the lower metal line exposed from the lower molding compound; and

a solder ball mounted on the under bump metallurgy.

11. A semiconductor package comprising:

a semiconductor chip whose bonding pad is disposed upwardly;

a metal wire whose one end is electrically connected to the bonding pad of the semiconductor chip;

a metal line deposited at a bottom face of the semiconductor chip and whose one end is electrically connected to the metal wire;

a molding compound for encapsulating an entire resultant such that the metal line is exposed therefrom thereby forming a ball land; and

a solder ball mounted on the ball land.

13. The method of claim 12, further comprising a step of forming an under bump metallurgy at the ball land.

12. A method for fabricating a semiconductor package comprising the steps of:

forming a trench at each portion between semiconductor chips constitute in a wafer;

depositing an upper metal line at an inner wall of the trench and on a bonding pad of the semiconductor chip;

encapsulating an upper portion of an entire resultant with the upper molding compound;

removing the wafer by a selected thickness by polishing so that a bottom face of the trench and the upper metal line are exposed;

electrically connecting the upper metal line and a lower metal line by depositing the lower metal line at a selected portion in a bottom face of the semiconductor chip;

encapsulating lower portion of an entire resultant with a lower molding compound so that a ball land to which the lower metal line is exposed, is formed;

mounting a solder ball on the ball land; and

separating the wafer into individual semiconductor chips by sawing the wafer along the trench.