FINE PITCH SYSTEM AND METHOD FOR REINFORCING BOND PADS IN SEMICONDUCTOR DEVICES

• US 20020089062A1
• Filed: 05/14/1999
• Published: 07/11/2002
• Est. Priority Date: 05/18/1998
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: MARTIN, CHARLES A., SARAN, MUKUL, COX, RONALD H.
• Granted Patent: US 6,448,650 B1
• Time in Patent Office: Days
• US Class Current: 257/759
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48647 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48724 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48747 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48824 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48847 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A reinforcing system and method of fabrication for a semiconductor integrated circuit bond pad comprises a first dielectric layer or stack disposed under the bond pad; at least one second dielectric layer or stack disposed under the first dielectric layer; and a reinforcing metal structure disposed into the second dielectric layer such that the patterns of the metal structure and the second dielectric layer comprise a uniformly flat interface towards the first dielectric layer. The patterns of the metal structure and the second dielectric layer comprise feature sizes and fine pitches used in the integrated circuit.

Claims

1. A reinforcing system for a semiconductor integrated circuit bond pad comprising:

a first dielectric layer disposed under said bond pad;

at least one second dielectric layer disposed under said first dielectric layer; and

a reinforcing structure disposed into said second dielectric layer such that the patterns of said structure and said second dielectric layer comprise a uniformly flat interface with said first dielectric layer.

2. The reinforcing system according to claim 1 wherein said patterns of said reinforcing structure and said second dielectric layer comprise dimensions and pitches used in said integrated circuit.

3. The reinforcing system according to claim 2 wherein said pattern dimensions of said reinforcing structure are selected relative to the material of said second dielectric layer such that said reinforcement is accomplished.

4. The reinforcing system according to claim 1 wherein said second dielectric layer includes areas filled by said reinforcing structure.

5. The reinforcing system according to claim 1 wherein said reinforcing structure occupies a substantial area under the bond pad.

6. The reinforcing system according to claim 1 wherein said reinforcing structure is mechanically stronger than said second dielectric layer.

7. The reinforcing system according to claim 1 wherein said second and said first dielectric layers are made of different dielectric materials.

8. The reinforcing system according to claim 1 wherein said second and said first dielectric layers are made of the same material.

9. The reinforcing system according to claim 1 wherein said second and said first dielectric layers are least one multi-layered dielectric stack.

10. The reinforcing system according to claim 1 wherein said first and second dielectric layers include an organic dielectric layer.

11. The reinforcing system according to claim 1 wherein said reinforcing structure is constructed of interconnecting of metal lines.

12. The reinforcing system according to claim 1 wherein said reinforcing structure includes alternating layers having parallel lines oriented generally perpendicularly with one another.

13. The reinforcing system according to claim 1 wherein said reinforcing structure includes a plurality of connected structural elements.

14. The reinforcing system according to claim 1 wherein said reinforcing structure includes a plurality of repeating structural elements.

15. The reinforcing system according to claim 1 wherein said reinforcing structure includes a plurality of repeating non-interconnected structural elements.

16. The reinforcing system according to claim 1 wherein said reinforcing structure includes a grid pattern.

17. The reinforcing system according to claim 1 wherein said reinforcing structure includes a repeating crucifix pattern.

18. The reinforcing system according to claim 1 wherein said reinforcing structure includes a honeycomb pattern.

19. The reinforcing system according to claim 1 wherein said reinforcing structure is connected to said bond pad by at least one via.

20. A reinforcing system for a semiconductor integrated circuit bond pad comprising:

a first dielectric stack disposed under said bond pad;

a second dielectric stack disposed under said first dielectric stack; and

a reinforcing structure disposed into said second dielectric stack such that the patterns of said reinforcing structure and said second dielectric stack comprise a uniformly flat interface towards said first dielectric stack.

21. The reinforcing system according to claim 20 wherein said dielectric stacks comprises multiple dielectric layers with said reinforcing metal structure disposed in at least one dielectric layer of said second dielectric stack.

22. The reinforcing system according to claim 20 wherein said patterns of said reinforcing structure and said second dielectric stack comprise feature sizes used in said integrated circuit.

23. The reinforcing system according to claim 20 wherein said reinforcing structure includes alternating layers having parallel lines oriented generally perpendicular with one another.

24. The reinforcing system according to claim 20 wherein said reinforcing structure includes a plurality of repeating connected structural elements.

25. The reinforcing system according to claim 20 wherein said reinforcing structure includes a plurality of repeating non-interconnected structural elements.

26. The reinforcing system according to claim 20 wherein said reinforcing structure includes a plurality of nested patterns.

27. The reinforcing system according to claim 20 wherein said reinforcing structure includes a spiral pattern.

29. The system according to claim 28 wherein lines of said dielectric layer comprise no meniscus towards respective neighboring lines of said reinforcing structure.

28. A reinforcing system for a semiconductor integrated circuit bond pad comprising:

a first dielectric layer disposed under said bond pad;

at least one second dielectric layer disposed under said first dielectric layer; and

a reinforcing structure disposed into said second dielectric layer such that the areas of said reinforcing structure are free of spurious material of said second dielectric layer, whereby the patterns of said reinforcing structure and said second dielectric layer remain discretely confined to their respective materials.

30. A method for reinforcing a bond pad in a semiconductor integrated circuit comprising:

forming a first dielectric layer;

patterning said first dielectric layer in a predetermined area into a predetermined pattern having a plurality of vacant areas;

forming a layer of reinforcing material above said patterned first dielectric layer, filling said vacant areas therein;

removing said reinforcing material except for said filled vacant areas, whereby a uniformly flat surface is formed and said first dielectric layer is transformed into a reinforcing layer;

forming a second dielectric layer above said uniformly flat surface of said reinforcing first dielectric layer; and

forming a bond pad on said second dielectric layer above said reinforcing first dielectric layer.

31. The method according to claim 30 wherein said first dielectric layer comprises the step of forming a mechanically weak dielectric layer.

32. The method according to claim 30 wherein said weak dielectric material in said first dielectric layer does not form any meniscus at the interfaces with said reinforcing metal.

33. The method according to claim 30 wherein said patterning step comprises the step of patterning said first dielectric layer with a repeating and interconnected pattern.

34. The method according to claim 30 wherein said patterning step comprises the step of patterning said first dielectric layer with a repeating and non-interconnected pattern.

35. The method according to claim 30 wherein said patterning step comprises the step of patterning said first dielectric layer with a nested configuration.

36. The method according to claim 30 wherein said patterning step comprises the step of patterning said first dielectric layer with feature sizes used in said integrated circuit.

37. The method according to claim 30 wherein said step of removing said reinforcing material except for said filled vacant areas comprises the step of discretely confining said reinforcing material into said vacant areas.

38. The method according to claim 30 wherein said step of removing said reinforcing material except for said filled vacant areas comprises the step of forming a substantially uniform flat surface of said patterned first dielectric layer and said filled vacant areas for forming said second dielectric layer.

39. The method according to claim 30 wherein said reinforcing material comprises a metal.

40. The method according to claim 30 further comprising the process of repeating the first dielectric layer forming, patterning, layer of reinforcing material forming, material removing, and second dielectric layer forming steps at least one time prior to forming said bond pad thereon.