Method and device for semiconductor wafer testing

• US 20020089345A1
• Filed: 01/05/2001
• Published: 07/11/2002
• Est. Priority Date: 01/05/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Doong, Yih-Yuh, Cheng, Jye-Yen, Charles, Ching-Hsiang Hsu
• Granted Patent: US 6,577,149 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A test structure for detecting defects in a semiconductor wafer and a method for using such test structure are provided. The test structure includes conduction units arranged in an array and test pads connecting to the conduction units. A conduction unit includes closely spaced or intermeshed conduction paths. The test pads are divided into X and Y groups. A pair of test pads X(i), X(i+1) are set to high voltage, a pair of test pads Y(j), Y(j+1) are set to low voltage, and the other test pads are floated. The current I(i,j) flowing from test pad pairs X to Y is measured. If current I(i,j) is a local minimum, then conduction unit (i,j) has a short circuit defect.

Claims

1. A test structure for detecting defects in a semiconductor wafer, comprising:

An array of conduction units, said array having an upper side, a lower side, a left side, and a right side;

a first set of test pads connected to conduction units situated along said left side of said array;

a second set of test pads connected to conduction units situated along said right side of said array;

a third set of test pads connected to conduction units situated along said upper side of said array;

a fourth set of test pads connected to conduction units situated along said lower side of said array;

a first set of conduction paths, each one of said first set of conduction paths running through a row of conduction units and connects one of said first set of test pads to one of said second set of test pads;

a second set of conduction paths, each one of said second set of conduction paths running through a column of conduction units and connects one of said third set of test pads to one of said fourth set of test pads;

wherein applying a predetermined set of test signals to said first, second, third, and fourth set of test pads, the location of a defect may be determined from the response signals measured from said first, second, third, and fourth set of test pads.

2. The test structure of claim 1, wherein said array of conduction units are labeled as U(i,j);

wherein said predetermined set of test signals includes a high voltage signal applied to one of said first set of test pads X(i) and one of said second set of test pads X(i+1), a low voltage signal applied to one of said third set of test pads Y(j) and one of said fourth set of test pads Y(j+1), and leaving the other test pads floating;

wherein the current I(i,j) flowing from test pads X(i), X(i+1) to test pads Y(j), Y(j+1) are measured and a short-circuit defect is detected at conduction unit U(i,j) if I(i,j) is a local current minimum.

3. The test structure of claim 1, wherein said conduction unit comprises intermeshed meander-style conduction paths.

4. The test structure of claim 3, wherein said conduction path comprises an upper path and a lower path, said upper path comprises of alternating segments of conductive segments and non-conductive segments, said lower path comprises of alternating segments of conductive segments and non-conductive segments, and said conductive segments of said upper path is connected to said conductive segments of said lower path by contact vias.

5. The test structure of claim 1, wherein said conduction unit comprises closely spaced meander-style conduction lines.

6. The test structure of claim 1, wherein said conduction unit comprises closely spaced comb-style conduction lines.