Programmable logic integrated circuit devices including dedicated processor components

• US 20020089348A1
• Filed: 10/02/2001
• Published: 07/11/2002
• Est. Priority Date: 10/02/2000
• Status: Abandoned Application

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Application Number:
  US09/969,977
• Publication Number:
  US 20020089348A1
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) processor object (or at least a high-functionality functional unit) for performing or at least helping to perform tasks that it is unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The processor object includes an operating portion and a program sequencer that retrieves or at least helps to retrieve instructions for controlling or at least partly controlling the operating portion. The processor object may also include an address generator and/or a multi-ported register file for generating or at least helping to generate addresses of data on which the operating portion is to operate and/or destinations of data output by the operating portions. Examples of typical operating portions include multiplier-accumulators, arithmetic logic units, barrel shifters, and DSP circuitry of these or other kinds. The PLD may be provided with the capability to allow programs to be written for the device using local or “relative” addresses, and to automatically convert these addresses to actual or “absolute” addresses when the programs are actually performed by the device.

Claims

1. A programmable logic device comprising:

programmable logic circuitry; and

a processor object including program sequencer circuitry adapted to select instruction information, and an operating portion responsive to the instruction information selected by the program sequencer circuitry.

2. The device defined in claim 1 wherein the processor object further includes address generator circuitry adapted to select data information.

3. The device defined in claim 2 wherein the operating portion is further responsive to the data information selected by the address generator circuitry.

4. The device defined in claim 1 further comprising:

memory circuitry adapted to store the instruction information.

5. The device defined in claim 4 wherein the memory circuitry is part of the programmable logic circuitry.

6. The device defined in claim 2 further comprising:

memory circuitry adapted to store the data information.

7. The device defined in claim 6 wherein the memory circuitry is part of the programmable logic circuitry.

8. The device defined in claim 2 wherein the address generator circuitry is further adapted to generate addresses of destinations for further data information output by the operating portion.

9. The device defined in claim 2 wherein the address generator comprises register file circuitry.

10. The device defined in claim 1 wherein the program sequencer circuitry is further adapted to automatically make a plurality of successive selections of instruction information.

11. The device defined in claim 2 wherein the address generator circuitry is further adapted to make a plurality of concurrent selections of data information.

12. The device defined in claim 1 wherein the processor object further includes register file circuitry adapted to select data information.

13. The device defined in claim 1 wherein the operating portion is selected from the group consisting of MAC circuitry, ALU circuitry, barrel shifter circuitry, and Galois Field circuitry.

14. The device defined in claim 1 wherein the operating portion includes multiple instances of circuitry selected from the group consisting of MAC circuitry, ALU circuitry, barrel shifter circuitry, and Galois Field circuitry.

15. The device defined in claim 1 further comprising:

circuitry adapted to convert instruction information selections that are relative to instruction information addresses that are absolute.

16. The device defined in claim 2 further comprising:

circuitry adapted to convert data information selections that are relative to data information addresses that are absolute.

17. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 1 coupled to the processing circuitry and the memory.

18. A printed circuit board on which is mounted a programmable logic device as defined in claim 1.

19. The printed circuit board defined in claim 18 further comprising:

a memory mounted on the printed circuit board and coupled to the programmable logic device.

20. The printed circuit board defined in claim 18 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.

21. A system comprising:

a programmable logic device including a processor object; and

circuitry external to the programmable logic device and adapted to apply signals to the programmable logic device for processing by that device, the signals including relative address information referring in relative terms to locations on the programmable logic device, the programmable logic device further including translation circuitry adapted to convert the relative address information to absolute address information identifying actual locations on the programmable logic device.

22. The system defined in claim 21 wherein the signals further include ID information associated with the relative address information, and wherein the translation circuitry is responsive to the ID information.

23. The system defined in claim 21 wherein the translation circuitry comprises:

address offset generation circuitry adapted to produce an address offset value; and

combinational circuitry adapted to combine the relative address information and the address offset value to produce the absolute address information.

24. The system defined in claim 23 wherein the combinational circuitry comprises:

adder circuitry adapted to add the address offset value to the relative address information to produce the absolute address information.

25. The system defined in claim 21 wherein the translation circuitry is further adapted to check validity of the absolute address information.

26. The system defined in claim 25 wherein the translation circuitry comprises compare circuitry adapted to compare the absolute address information to permissible address information.

28. The device defined in claim 27 wherein the processor object circuitry comprises:

program sequencer circuitry;

address generator circuitry; and

operating portion circuitry.

29. The device defined in claim 28 wherein the program sequencer circuitry is adapted to retrieve from the memory circuitry instructions for at least partly controlling operation of the operating portion circuitry.

30. The device defined in claim 28 wherein the address generator circuitry is adapted to retrieve from the memory circuitry data on which the operating portion circuitry operates.

31. The device defined in claim 28 wherein the address generator circuitry is adapted to identify locations in the memory circuitry to receive data output by the operating portion circuitry.

32. The device defined in claim 28 wherein the address generator circuitry comprises multi-ported register file circuitry.

33. The device defined in claim 28 wherein the soft-logic portion is adapted to provide signals for at least partly controlling operation of the program sequencer circuitry.

34. The device defined in claim 33 wherein the signals are indicative of an instruction address for use by the program sequencer circuitry.

35. The device defined in claim 34 wherein the program sequencer circuitry is adapted to respond to the instruction address by producing a succession of identifications of locations in the memory circuitry.

36. The device defined in claim 28 wherein the soft-logic portion is adapted to provide signals for at least partly controlling operation of the address generator circuitry.

37. The device defined in claim 36 wherein the signals are indicative of a data address for use by the address generator circuitry.

38. The device defined in claim 37 further comprising:

interface circuitry adapted to convert the data address to an absolute address in the memory circuitry.

39. The device defined in claim 28 wherein the address generator circuitry is adapted to identify in parallel a plurality of locations in the memory circuitry.

40. The device defined in claim 28 wherein the operating portion circuitry is selected from the group consisting of MAC circuitry, ALU circuitry, barrel shifter circuitry, and Galois Field circuitry.

41. The device defined in claim 28 wherein the operating portion circuitry comprises multiple instances of circuitry selected from the group consisting of MAC circuitry, ALU circuitry, barrel shifter circuitry, and Galois Field circuitry.

42. The device defined in claim 28 wherein the operating portion is adapted to execute a VLIW instruction.

43. The device defined in claim 28 wherein the operating portion is adapted to perform at least one DSP operation.

27. A programmable logic device comprising:

a soft-logic portion including programmable logic circuitry, memory circuitry, and programmable interconnection circuitry; and

a hard-logic portion connected to the soft-logic portion and including processor object circuitry.

44. A programmable logic device comprising:

programmable logic circuitry; and

an at least partly hard-wired, high functionality, functional unit adapted to exchange signal information with the programmable logic circuitry.

45. The programmable logic device defined in claim 44 wherein the functional unit is adapted to perform functions selectable from a plurality of functions.

46. The programmable logic device defined in claim 45 wherein the functional unit is programmable to select the functions that it will perform from the plurality of functions.

47. The programmable logic device defined in claim 45 wherein the functional unit is dynamically controllable by a control signal to select the functions that it will perform from the plurality of functions.

48. The programmable logic device defined in claim 47 wherein the programmable logic circuitry is adapted to supply the control signal.

49. The programmable logic device defined in claim 45 wherein the functional unit is programmable to select the functions that it will perform from the plurality of functions based on either a programmable selection or a dynamic control signal selection.

50. The programmable logic device defined in claim 49 wherein the programmable logic circuitry is adapted to supply the control signal.

51. The programmable logic device defined in claim 44 wherein the functional unit is selected from the group consisting of MAC circuitry, ALU circuitry, barrel shifter circuitry, and Galois Field circuitry.

52. The programmable logic device defined in claim 44 wherein the programmable logic circuitry includes memory circuitry.

53. The programmable logic device defined in claim 52 wherein the memory circuitry is adapted to store data for processing by the functional unit.

54. The programmable logic device defined in claim 52 wherein the memory circuitry is adapted to store program instructions for execution at least in part by the functional unit.

55. The programmable logic device defined in claim 53 wherein the programmable logic circuitry is adapted to select data from the memory circuitry for application to the functional unit.

56. The programmable logic device defined in claim 54 wherein the programmable logic circuitry is adapted to select program instructions from the memory circuitry for execution by the functional unit.

57. The programmable logic device defined in claim 56 wherein the programmable logic circuitry is further adapted to use an instruction selected from the memory circuitry to at least partly control selection of data on which the functional unit operates.

58. The programmable logic device defined in claim 56 wherein the programmable logic circuitry is further adapted to use an instruction selected from the memory circuitry to at least partly control functions performed by the functional unit.