Method and resulting device for manufacturing for double gated transistors

• US 20020090758A1
• Filed: 09/18/2001
• Published: 07/11/2002
• Est. Priority Date: 09/19/2000
• Status: Abandoned Application

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: Henley, Francois J., Cheung, Nathan
• Application Number:
  US09/956,486
• Publication Number:
  US 20020090758A1
• Time in Patent Office: Days
• US Class Current: 438/110
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26593 at a temperature lower than room temperature
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

A process for forming an integrated circuit device structure. The process includes forming a first gate layer on a thickness of material on a donor substrate. The donor substrate has a cleave region underlying the gate layer. The process also includes joining the donor substrate to a handle substrate where the gate layer face the handle substrate; and separating the thickness of material at the cleave region from the donor substrate to define a handle substrate comprising the gate layer and an overlying thickness of material. The process forms a plurality of second gate structures on the thickness of material, where at least one of the first gate structures facing one of the second gate structures forming a channel region therebetween.

Claims

1. A process for forming an integrated circuit device structure, said process comprising:

forming a plurality of first gate structures on a thickness of material on a donor substrate, the donor substrate comprising a cleave region underlying the plurality of gate structures, the cleave region comprising a deposited layer, each of the gate structures having a substantially planar upper surface;

joining the donor substrate to a handle substrate where the plurality of gate structures including the planar upper surface face the handle substrate;

separating the thickness of material at the cleave region from the donor substrate to define a handle substrate comprising the plurality of gate structures and the overlying thickness of material; and

forming a plurality of second gate structures on the thickness of material, at least one of the first gate structures facing one of the second gate structures to form a channel region therebetween.

2. The process of claim 1 wherein the deposited layer comprises silicon germanium.

3. The process of claim 2 wherein the deposited layer further comprises an epitaxial layer.

4. The process of claim 1 wherein the cleave region is derived from layer formed by physical vapor deposition or chemical vapor deposition.

5. The process of claim 1 wherein the separating step is provided by a controlled cleaving action to remove the thickness of material from the donor substrate.

6. The process of claim 1 wherein the donor substrate is a silicon wafer.

7. The process of claim 1 wherein the cleave region further comprises an implanted region comprising hydrogen bearing particles.

8. The process of claim 1 wherein the donor substrate is made of a material selected from the group consisting of silicon, diamond, quartz, glass, sapphire, silicon carbide, dielectric, group III/V material, plastic, ceramic material, and multilayered substrate.

9. The process of claim 1 wherein the donor substrate is planar.

10. The process of claim 1 wherein the donor substrate is curved.

11. A multi-gate MOS transistor structure comprising:

a handle substrate;

a gate region defined overlying the handle substrate;

a first gate dielectric region defined overlying the gate region;

a cleaved region forming a channel region defined overlying the first gate dielectric region and defined overlying the first gate region, the cleaved region having a thickness of less than 250 nm and having a uniformity of 1-10%;

a second gate dielectric region defined overlying the channel region;

a second gate region defined overlying the second gate dielectric region and defined overlying the channel region, whereupon the second gate opposes the first gate and has the channel region defined between the first gate and the second gate.

12. The transistor structure of claim 11 wherein the cleaved region is provided by a controlled cleaving process.

14. The method of claim 13 wherein the etching process comprises an anisotropic etching process.

15. The method of claim 13 wherein the first gate structure and second gate structure define a double gated MOS transistor.

16. The method of claim 13 wherein the channel region has a length of less than 100 nm.

17. The method of claim 13 wherein the channel region has a length ranging from about 25 nm to about 100 nm.

18. The method of claim 13 wherein the patterning self aligns the first gate structure with the second gate structure.

19. The method of claim 13 further comprising connecting the first gate structure with the second gate structure through a via structure.

20. The method of claim 13 further comprising connecting the first gate structure to another gate structure.

13. A process for forming an integrated circuit device structure, said process comprising:

forming a first gate layer on a thickness of material on a donor substrate, the donor substrate comprising a cleave region underlying the first gate layer, the first gate layer having a substantially planar upper surface;

joining the donor substrate to a handle substrate where the first gate layer including the planar upper surface face the handle substrate;

separating the thickness of material at the cleave region from the donor substrate to define a handle substrate comprising the first gate layer and the overlying thickness of material;

forming a second gate layer overlying the thickness of material to define a sandwiched structure including the first gate layer, the detached thickness of material, and second gate layer; and

patterning the sandwiched structure to define a first gate structure from the first gate layer defined opposite of a second gate structure from the second gate layer using at least an etching process where upon a channel region is defined from the detached and patterned thickness of material defined between the first gate structure and the second gate structure.