Package with low stress hermetic seal

• US 20020090761A1
• Filed: 01/22/2002
• Published: 07/11/2002
• Est. Priority Date: 12/07/2000
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Eric Daniel Perfecto, Hilton T. Toy, Lewis Sigmund Goldmann, Raed A. Sherif, William Frederick Shutler
• Inventors: Sherif, Raed A., Shutler, William Frederick, Goldmann, Lewis Sigmund, Toy, Hilton T., Perfecto, Eric Daniel
• Granted Patent: US 6,459,160 B1
• Time in Patent Office: Days
• US Class Current: 438/124
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16315 Shape

Abstract

A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.

Claims

1. A method of forming a sealed electronic circuit package comprising:

providing a substrate having a top surface and a cover having a mating surface confronting the top surface of the substrate,

forming a seal at the peripheral edge of the substrate between the substrate and the mating surface of the cover by the steps as follows;

a) forming a peripheral substrate non-metallic soft frame on the top surface of the substrate having a top soft frame surface which faces upwardly,

b) providing a cover frame surface on the mating surface of the cover which is exposed downwardly,

c) forming a lower adhesion frame over the soft frame, and

d) joining the top surface of the lower adhesion frame and the cover frame surface with solder to form a hermetic via-seal to the substrate frame surface forming a seal between the cover frame surface and the substrate.

2. The method of claim 1 with the channel and the via-seal are located laterally aside from the confronting portions of the surfaces of the cover and the substrate.

3. The method of claim 1 with the via-seal being exposed on the surface of the soft layer on an exterior surface of the peripheral substrate frame.

4. The method of claim 1 with the via-seal being exposed on the surface of the soft layer on an interior surface of the peripheral substrate frame.

5. The method of claim 1 with the substrate being a ceramic chip carrier and the soft layer being a polymer.

6. The method of claim 1 with the substrate being a ceramic chip carrier and the soft layer being a polyimide polymer.

7. The method of claim 1 with the substrate being a glass ceramic chip carrier and the soft layer being a polymer.

8. The method of claim 1 with the substrate being a glass ceramic chip carrier and the soft layer being a polyimide polymer.

9. The method of claim 1 with the substrate being a glass ceramic chip carrier and the soft layer being a polyimide polymer and the lower adhesion frame is composed of laminated Cr—

Ni—

Au layers

10. The method of claim 1 with the soft layer has a thickness less than or equal to about 12 μ

m.

11. The method of claim 1 including:

forming the non-metallic soft frame with a central channel extending down through the non-metallic soft layer to expose a portion of the substrate frame surface below the channel with the lower adhesion frame extending down through the channel formed in the nonmetallic soft layer to contact the substrate surface,

whereby the hermetic via-seal extends through the channel to the substrate frame surface to form a seal between the cover frame surface and the substrate.

12. The method of claim 1 wherein the solder has a melting point 30°

C. to 40°

C. below the melting point of C4 below the softening point of any solders or polymers inside the package.

13. The method of claim 1 wherein the solder is selected from the group consisting of an (SnAg or a SnAgCu solder with about 96%Sn) or a two-material (lead/tin eutectic) solder.

14. The method of claim 1 including:

forming the lower adhesion frame with an extension across the edge of the non-metallic soft layer to contact the substrate surface at a distal location,

whereby the hermetic via-seal extends across the edge of the soft layer to form a seal between the cover frame surface and the substrate.

16. The method of claim 15 wherein the solder has a melting point 30°

C. to 4020 C. below the melting point of C4 below the softening point of any solders or polymers inside the package.

17. The method of claim 15 wherein the solder is selected from the group consisting of an (SnAg or a SnAgCu solder with about 96%Sn) or a two-material (lead/tin eutectic) solder.

19. The package of claim 18 with the channel and the via-seal located laterally aside from the confronting surfaces of the cover and substrate.

20. The package of claim 18 with the via-seal exposed on the surface of the soft layer on an exterior surface of the peripheral substrate frame.

21. The package of claim 18 with the via-seal exposed on the surface of the soft layer on an interior surface of the peripheral substrate frame.

22. The package of claim 18 with the substrate being a ceramic chip carrier and the soft layer being a polymer.

23. The package of claim 18 with the substrate being a ceramic chip carrier and the soft layer being a polyimide polymer.

24. The package of claim 18 with the substrate being a glass ceramic chip carrier and the soft layer being a polymer.

25. The package of claim 18 with the substrate being a glass ceramic chip carrier and the soft layer being a polyimide polymer.

26. The package of claim 18 with the substrate being a glass ceramic chip carrier and the soft layer being a polyimide polymer and the lower adhesion frame being composed of laminated Cr—

Ni—

Au layers.

27. The package of claim 18 with the soft layer has a thickness ≦

about 12 μ

m.

28. The package of claim 18 with the non-metallic soft frame having a central channel formed down through the non-metallic soft layer to expose a portion of the substrate frame surface below the channel with the lower adhesion frame extending down through the channel formed in the non-metallic soft layer to contact the substrate surface, whereby the hermetic via-seal extends through the channel to the substrate frame surface to form a seal between the cover frame surface and the substrate.

30. The package of claim 18 wherein the solder has a melting point 30°

C. to 40°

C. below the melting point of C4 below the softening point of any solders or polymers inside the package.

31. The package of claim 18 wherein the solder is selected from the group consisting of an (SnAg or a SnAgCu solder with about 96%Sn) or a two-material (lead/tin eutectic) solder.

15. A method of forming a sealed electronic circuit package comprising:

providing a substrate having a top surface and a cover having a mating surface confronting the top surface of the substrate,

forming a seal at the peripheral edge of the substrate between the substrate and the mating surface of the cover by the steps as follows;

a) forming a peripheral substrate non-metallic soft frame formed on the top surface of the substrate having a top soft frame surface which faces upwardly with a central channel formed down through the non-metallic soft layer to expose a portion of the substrate frame surface below the channel,

b) forming a cover frame for providing adhesion formed on the mating surface of the cover, the cover frame having a cover frame surface which is exposed downwardly,

c) forming a lower adhesion frame over the soft frame extending down through the channel formed in the non-metallic soft layer to contact the substrate surface, and

d) joining the top surface of the lower adhesion frame and the cover frame surface with solder and extending into the channel to form a hermetic via-seal through the channel to the substrate frame surface forming a seal between the cover frame surface and the substrate extending through the channel in the soft frame.

18. A sealed electronic circuit package comprising:

a substrate having a top surface,

a cover having a mating surface confronting the top surface of the substrate,

a seal at the peripheral edge of the substrate between the substrate and the mating surface of the cover,

the seal including as follows;

a) a peripheral substrate non-metallic soft frame formed on the top surface of the substrate having a top soft frame surface which faces upwardly,

b) a cover frame for providing adhesion formed on the mating surface of the cover, the cover frame having a cover frame surface which is exposed downwardly,

c) a lower adhesion frame formed over the soft frame extending, and

d) solder joining the top surface of the lower adhesion frame and the cover frame surface to form a hermetic via-seal.

29. The package of claim 18:

with the lower adhesion frame extending across the edge of the non-metallic soft layer to contact the substrate surface at a distal location,

whereby the hermetic via-seal extends across the edge of the soft layer to form a seal between the cover frame surface and the substrate.

32. A sealed electronic circuit package comprising:

a substrate having a top surface,

a cover having a mating surface confronting the top surface of the substrate,

a seal at the peripheral edge of the substrate between the substrate and the mating surface of the cover,

the seal including as follows;

a) a non-metallic soft layer formed the top surface of the substrate for providing adhesion, at the peripheral edge of the substrate, the substrate frame having a top surface facing upwardly,

b) a cover frame for providing adhesion formed on the mating surface of the cover having a cover frame surface facing downwardly,

c) an intermediate adhesion layer formed on the upper surface of the soft layer, the intermediate adhesion layer having an upper surface, and

d) solder formed between the intermediate adhesion layer upper surface and the cover frame surface.

33. The package of claim 32 with the substrate being a ceramic chip carrier and the soft layer being a polymer.

34. The package of claim 32 with the substrate being a ceramic chip carrier and the soft layer being a polyimide polymer.

35. The package of claim 32 with the substrate being a glass ceramic chip carrier and the soft layer being a polymer.

36. The package of claim 32 with the substrate being a glass ceramic chip carrier and the soft layer being a polyimide polymer.

37. The package of claim 32 with the substrate being a glass ceramic chip carrier and the soft layer being a polyimide polymer and the intermediate adhesion layer being composed of laminated Cr—

Ni—

Au layers and the cover frame being coated with laminated Mo—

Ni—

Au layers.

38. The package of claim 32 with the soft layer has a thickness ≦

about 12 μ

m.

39. The package of claim 32 wherein the solder has a melting point 30°

C. to 40°

C. below the melting point of C4 below the softening point of any solders or polymers inside the package.

40. The package of claim 32 wherein the solder is selected from the group consisting of an (SnAg or a SnAgCu solder with about 96%Sn) or a two-material (lead/tin eutectic) solder.

41. A sealed electronic circuit package comprising:

a substrate having a top surface,

a cover having a mating surface confronting the top surface of the substrate,

a seal at the peripheral edge of the substrate between the substrate and the mating surface of the cover,

the seal including as follows;

a) a peripheral substrate non-metallic soft frame formed on the top surface of the substrate having a top soft frame surface which faces upwardly with a central channel formed down through the non-metallic soft layer to expose a portion of the substrate frame surface below the channel,

b) a cover frame for providing adhesion formed on the mating surface of the cover, the cover frame having a cover frame surface which is exposed downwardly,

c) a lower adhesion frame formed over the soft frame extending down through the channel formed in the non-metallic soft layer to contact the substrate surface, and

d) solder joining the top surface of the lower adhesion frame and the cover frame surface and extending into the channel to form a hermetic via-seal through the channel to the substrate frame surface forming a seal between the cover frame surface and the substrate extending through the channel in the soft frame.

42. The package of claim 41 wherein the solder has a melting point 30°

C. to 40°

C. below the melting point of C4 below the softening point of any solders or polymers inside the package.

43. The package of claim 41 wherein the solder is selected from the group consisting of an (SnAg or a SnAgCu solder with about 96%Sn) or a two-material (lead/tin eutectic) solder.