Self-test electronic assembly and test system

• US 20020091966A1
• Filed: 03/14/2002
• Published: 07/11/2002
• Est. Priority Date: 07/19/1999
• Status: Active Grant

• Current Assignee: TiVo Solutions Inc. (Adeia Inc.)
• Original Assignee: David Platt, James M. Barton, Shahin Tahmassebi
• Inventors: Tahmassebi, Shahin, Platt, David, Barton, James M.
• Granted Patent: US 6,643,798 B2
• Time in Patent Office: Days
• US Class Current: 714/25
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/2268 Logging of test results
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 11/2635 using a storage for the test inputs, e.g. test ROM, script files

Abstract

A self-test electronic assembly performs self-testing, such as diagnostic or run-in testing of components and circuits, based upon internally stored test procedures. The results of self-testing are stored internally to the device, providing valuable information regarding the self-test electronic assembly, both during the manufacturing process, and preferably for ongoing in-situ operation. A test system is preferably linked to one or more self-test electronic assemblies, and provides loopback circuitry for each installed self-test electronic assembly, whereby the self-test electronic assemblies can further test components, circuitry, and security encoding and decoding operation. The preferred test rack also provides efficient and consistent monitoring and quality control over the self-testing of self-test electronic assemblies. During in-situ operation, the self-test electronic assemblies preferably monitor operating parameters, and continue to periodically perform self-testing, while storing the information within the device, and preferably transmitting the information to an external location.

Claims

1. A process for creating a security key pair in a secure microprocessor system, comprising the steps of:

providing a memory device coupled to said microprocessor;

wherein said microprocessor generates a security key pair comprising a private key and a public key;

storing said private key in said memory device;

sending said public key to an external receiver; and

disabling changes to said memory device after said public key is transmitted.

2. The process of claim 1, wherein said public key is used to access said secure microprocessor system;

and wherein said private key is not distributed outside of said secure microprocessor system.

3. The process of claim 1, further comprising the step of:

providing communication means on said secure microprocessor system for communicating information between said secure microprocessor system and said external receiver.

4. A process for creating a security key pair in a secure microprocessor system, comprising the steps of:

providing a memory device coupled to said microprocessor;

generating a security key pair comprising a private key and a public key;

providing storage means for storing said private key in said memory device;

storing said public key on a server; and

providing memory disabling means for disabling changes to said memory device after said private key is stored.

5. The process of claim 4, wherein said public key is used to access said secure microprocessor system;

and wherein said private key is not distributed outside of said secure microprocessor system.

6. The process of claim 4, further comprising the step of:

providing communication means on said secure microprocessor system for communicating information between said secure microprocessor system and said server.

7. A process for creating a security key pair for a secure computer system, comprising the steps of:

providing a memory device on said computer system;

generating a security key pair comprising a private key and a public key;

storing said private key in said memory device;

sending said public key to a server; and

providing memory disabling means for disabling changes to said memory device after said private key is stored.

8. The process of claim 7, wherein said public key is used to access said secure computer system;

and wherein said private key is not distributed outside of said secure computer system.

9. The process of claim 7, further comprising the step of:

providing communication means on said secure computer system for communicating information between said secure computer system and said server.

10. A process for creating a security key pair in a secure microprocessor system, comprising the steps of:

providing a memory device coupled to said microprocessor;

downloading security software into said memory device;

wherein said microprocessor executes said security software and generates a security key pair comprising a private key and a public key;

storing said private key in said memory device;

sending said public key to an external receiver; and

providing memory disabling means for disabling changes to said memory device after said public key is transmitted.

11. The process of claim 10, wherein said public key is used to access said secure microprocessor system;

and wherein said private key is not distributed outside of said secure microprocessor system.

12. The process of claim 10, further comprising the step of:

providing communication means on said secure microprocessor system for communicating information between said secure microprocessor system and said external receiver.

14. The apparatus of claim 13, wherein said public key is used to access said secure microprocessor system;

and wherein said private key is not distributed outside of said secure microprocessor system.

15. The apparatus of claim 13, further comprising:

communication means on said secure microprocessor system for communicating information between said secure microprocessor system and said external receiver.

17. The apparatus of claim 16, wherein said public key is used to access said secure microprocessor system;

and wherein said private key is not distributed outside of said secure microprocessor system.

18. The apparatus of claim 16, further comprising:

communication means on said secure microprocessor system for communicating information between said secure microprocessor system and said server.

20. The apparatus of claim 19, wherein said public key is used to access said secure computer system;

and wherein said private key is not distributed outside of said secure computer system.

21. The apparatus of claim 19, further comprising:

communication means on said secure computer system for communicating information between said secure computer system and said server.

13. An apparatus for creating a security key pair in a secure microprocessor system, comprising:

a memory device coupled to said microprocessor;

wherein said microprocessor generates a security key pair comprising a private key and a public key;

a module for storing said private key in said memory device;

a module for sending said public key to an external receiver; and

a module for disabling changes to said memory device after said public key is transmitted.

16. An apparatus for creating a security key pair in a secure microprocessor system, comprising:

a memory device coupled to said microprocessor;

key generation means for generating a security key pair comprising a private key and a public key;

storage means for storing said private key in said memory device;

a module for storing said public key on a server; and

memory disabling means for disabling changes to said memory device after said private key is stored.

19. An apparatus for creating a security key pair for a secure computer system, comprising:

a memory device on said computer system;

a module for generating a security key pair comprising a private key and a public key;

a module for storing said private key in said memory device;

a module for sending said public key on a server; and

memory disabling means for disabling changes to said memory device after said private key is stored.

22. An apparatus for creating a security key pair in a secure microprocessor system, comprising:

a memory device coupled to said microprocessor;

a module for downloading security software into said memory device;

wherein said microprocessor executes said security software and generates a security key pair comprising a private key and a public key;

a module for storing said private key in said memory device;

a module for sending said public key to an external receiver; and

memory disabling means for disabling changes to said memory device after said public key is transmitted.

23. The apparatus of claim 22, wherein said public key is used to access said secure microprocessor system;

and wherein said private key is not distributed outside of said secure microprocessor system.

24. The apparatus of claim 22, further comprising:

communication means on said secure microprocessor system for communicating information between said secure microprocessor system and said external receiver.