Process window based optical proximity correction of lithographic images

• US 20020091986A1
• Filed: 01/11/2001
• Published: 07/11/2002
• Est. Priority Date: 01/11/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Liebmann, Lars W., Wong, Alfred K., Lavin, Mark A., Ferguson, Richard A.
• Granted Patent: US 6,578,190 B2
• Time in Patent Office: Days
• US Class Current: 716/53
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging

Abstract

A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

Claims

1. A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate, the method comprising:

providing a mask pattern of a feature to be created on the substrate using the mask;

establishing target dimensional bounds of the pattern;

determining simulated achievable dimensional bounds of the pattern;

comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern; and

determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern.

2. The method of claim 1 wherein the feature is an integrated circuit on a semiconductor substrate.

3. The method of claim 1 wherein target dimensional bounds of the pattern are established by determining maximum variations in pattern edge placement which still provide adequate pattern feature performance.

4. The method of claim 1 wherein simulated achievable dimensional bounds of the pattern are established by determining optical proximity effects of the feature pattern on the mask during lithographic production.

5. The method of claim 1 wherein simulated achievable dimensional bounds of the pattern are established by determining lithographic process variations during lithographic production.

6. The method of claim 5 wherein simulated achievable dimensional bounds of the pattern are established by determining variations in lithographic dosage through the mask during lithographic production.

7. The method of claim 5 wherein simulated achievable dimensional bounds of the pattern are established by determining variations in lithographic focus through the mask during lithographic production.

8. The method of claim 5 wherein simulated achievable dimensional bounds of the pattern are established by determining variations in etching during lithographic production.

9. The method of claim 1 further including modifying lithographic process conditions to reduce the locations where the simulated achievable dimensional bounds of the pattern exceed the target dimensional bounds of the pattern.

10. The method of claim 5 further including reviewing lithographic process conditions to ensure that widths of the simulated achievable dimensional bounds are narrower than widths of target dimensional bounds for corresponding portions of the feature pattern.

11. The method of claim 1 further including modifying the mask feature pattern to reduce the locations where the simulated achievable dimensional bounds of the pattern exceed the target dimensional bounds of the pattern.

12. The method of claim 1 further including modifying the mask feature pattern to ensure that the simulated achievable dimensional bounds are within the target dimensional bounds for the feature pattern.

13. The method of claim 1 wherein the target dimensional bounds are determined from theoretical design rules.

14. The method of claim 1 wherein the target dimensional bounds are determined from empirical experimental data.

15. The method of claim 1 wherein the simulated achievable dimensional bounds are determined from first principle modeling.

16. The method of claim 1 wherein the simulated achievable dimensional bounds are determined from empirical measurements.

17. The method of claim 1 wherein the target dimensional bounds and simulated achievable dimensional bounds are represented by a band showing ranges of feature edges.

18. The method of claim 1 wherein the target dimensional bounds and simulated achievable dimensional bounds are represented by lines showing maximum and minimum feature edges.

19. The method of claim 1 wherein determining the locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern includes calculating total area of the simulated achievable dimensional bounds outside of the acceptable target dimensional bounds.

20. The method of claim 19 wherein the target dimensional bounds and simulated achievable dimensional bounds are represented by pixels, and wherein calculating total area of the simulated achievable dimensional bounds outside of the acceptable target dimensional bounds is by determining the sum of all pixels outside of the acceptable target dimensional bounds.

21. A method of creating a pattern for a mask adapted for use in lithographic production of integrated circuits on a semiconductor substrate, the method comprising:

providing a mask pattern of a feature to be created on the semiconductor substrate using the mask; and

modifying lithography process exposure dose and focus conditions and/or the mask pattern to maximize the usable range of exposure dose and focus conditions in the lithographic production.

22. A method of creating a pattern for a mask adapted for use in lithographic production of integrated circuits on a semiconductor substrate, the method comprising:

providing a mask pattern of a feature to be created on the semiconductor substrate using the mask;

establishing target dimensional bounds of the pattern; and

modifying the mask pattern such that the resulting image of the mask pattern created on the semiconductor substrate falls within the target dimensional bounds of the pattern.

23. A method of creating a pattern for a mask adapted for use in lithographic production of integrated circuits on a semiconductor substrate, the method comprising:

providing a mask pattern of a feature to be created on the semiconductor substrate using the mask;

determining simulated achievable dimensional bounds of the pattern; and

modifying the mask pattern such that the resulting image of the mask pattern created on the semiconductor substrate falls within the simulated achievable dimensional bounds of the pattern.

24. A computer program product for creating a pattern for a mask adapted for use in lithographic production of integrated circuits on a semiconductor substrate, the mask pattern being of a feature to be created on the substrate using the mask, said computer program product having:

computer readable program code means for establishing target dimensional bounds of the pattern;

computer readable program code means for;

determining simulated achievable dimensional bounds of the pattern;

comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern; and

computer readable program code means for determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern.

25. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for creating a pattern for a mask adapted for use in lithographic production of integrated circuits on a semiconductor substrate, the mask pattern being of a feature to be created on the substrate using the mask, said method steps comprising:

establishing target dimensional bounds of the pattern;

determining simulated achievable dimensional bounds of the pattern;

comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern; and

determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern.