Adaptively calibrating analog-to-digital conversion with correction table indexing

• US 20020093439A1
• Filed: 09/26/2001
• Published: 07/18/2002
• Est. Priority Date: 11/20/1998
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Handel, Peter, Skoglund, Mikael, Lundin, Henrik
• Granted Patent: US 6,690,311 B2
• Time in Patent Office: Days
• US Class Current: 341/120
• CPC Class Codes: H03M 1/1004 without interrupting normal operation, e.g. by providing an additional component for temporarily replacing components to be tested or calibrated H03M1/1009, H03M1/1071 take precedence
• CPC Class Codes: H03M 1/1038 by storing corrected or correction values in one or more digital look-up tables H03M1/1057 takes precedence
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

Methods, systems, and arrangements enable true wide-band calibration of analog-to-digital conversion (ADC) using correction table indexing. The frequency of an analog input signal that corresponds to a digital output sample is accounted for, at least partially, when accessing a correction table during the creation and use thereof. For example, in addition to at least a portion of a current sample, at least portion(s) of previous and/or subsequent samples may be used to build (e.g., by bit concatenation) an index for addressing a correction table memory. In effect, compensation may be achieved for ADC errors that are frequency dependent. This correction table indexing may advantageously be employed along with a scheme that estimates one or more parameters of the analog input signal in the digital domain on a sample-by-sample basis in order to reconstruct the analog input signal in the digital domain.

Claims

1. An apparatus that includes a signal processing device, the signal processing device comprising:

an analog-to-digital converter (ADC), said ADC having at least one analog input and at least one digital output;

a first processor, said first processor for adaptively estimating at least one first parameter relating to the at least one analog input of said ADC, the at least one first parameter being estimated based, at least partly, on the at least one digital output of said ADC;

a filter, said filter having an input coupled to the at least one digital output of said ADC and receiving the at least one first parameter, said filter including a plurality of coefficients that adapt to minimize a noise gain of said filter; and

a second processor, said second processor for building concatenated indices from various time lags of the at least one digital output of said ADC.

2. The apparatus according to claim 1, wherein the signal processing device further comprises:

a third processor, said third processor for computing at least one second parameter relating an output of said filter to the input of said filter; and

a fourth processor, said fourth processor for computing a correction table in dependence upon the output of said filter and the concatenated indices.

3. The apparatus according to claim 2, wherein the signal processing device further comprises:

a fifth processor, said fifth processor for outputting a calibrated value from said correction table based, at least partly, on a functional analog input and at least one concatenated index.

4. The apparatus according to claim 2, wherein the at least one second parameter comprises a signal-to-noise and distortion ratio (SINAD) of said filter.

5. The apparatus according to claim 2, wherein at least one of said first, second, third, and fourth processors comprise one or more software modules.

6. The apparatus according to claim 1, wherein the various time lags comprise at least one past time differential, at least one future time differential, or both at least one past and at least one future time differential.

7. The apparatus according to claim 1, wherein the at least one digital output of said ADC comprises a plurality of digital outputs of said ADC, and the concatenated indices are built using at least portions of the plurality of digital outputs of said ADC.

8. A method for calibrating analog-to-digital conversion (ADC), comprising the steps of:

converting an analog signal to a digital signal, the digital signal including at least one sample;

producing an index value from the at least one sample and at least one of a previous sample and a subsequent sample; and

updating a correction table responsive to the index value.

9. The method according to claim 8, wherein said step of updating a correction table responsive to the index value comprises the step of updating the correction table at a location responsive to the index value using another value that is based, at least partly, on the at least one sample.

10. The method according to claim 8, wherein said step of updating a correction table responsive to the index value comprises the step of updating the correction table responsive to a history of samples, each sample of the history of samples corresponding to the index value.

11. The method according to claim 8, wherein said step of producing an index value from the at least one sample and at least one of a previous sample and a subsequent sample comprises the step of concatenating a plurality of bits associated with the at least one sample and the at least one of the previous sample and the subsequent sample.

12. The method according to claim 11, wherein the at least one sample is comprised of a first plurality of bits, the at least one of the previous sample and the subsequent sample is comprised of a second plurality of bits, and the plurality of bits concatenated in said step of concatenating a plurality of bits is comprised of at least a first portion of the first plurality of bits and at least a second portion of the second plurality of bits.

13. The method according to claim 12, wherein the plurality of bits concatenated in said step of concatenating a plurality of bits is comprised of all of the first plurality of bits and all of the second plurality of bits.

14. The method according to claim 12, wherein a first number of bits corresponding to the first portion of the first plurality of bits differs from a second number of bits corresponding to the second portion of the second plurality of bits.

15. The method according to claim 8, further comprising the steps of:

recursively estimating at least one parameter of the analog signal based, at least partly, on the at least one sample;

adaptively reconstructing the analog signal in the digital domain based, at least partly, on the at least one parameter;

determining whether the reconstruction has converged;

if so, executing said step of updating a correction table responsive to the index value; and

if not, then not executing said step of updating a correction table responsive to the index value, for at least the at least one sample.

16. The method according to claim 8, wherein the analog signal comprises an analog calibration signal that steps through a plurality of frequencies.

18. The method according to claim 17, wherein the analog signal comprises a functional signal.

19. The method according to claim 17, wherein said step of producing an index value from the at least one sample and at least one of a previous sample and a subsequent sample comprises at least one of the following steps:

producing the index value from the at least one sample and a plurality of previous samples;

producing the index value from the at least one sample and a plurality of subsequent samples; and

producing the index value from the at least one sample and a plurality of previous samples and a plurality of subsequent samples.

20. The method according to claim 17, further comprising the step of:

accumulating a history of samples produced as a result of said step of converting an analog signal to a digital signal, the history of samples comprising the at least one sample and the at least one of a previous sample and a subsequent sample.

21. The method according to claim 20, wherein said step of producing an index value from the at least one sample and at least one of a previous sample and a subsequent sample comprises the step of producing the index value from the history of samples.

22. The method according to claim 21, wherein said step of producing the index value from the history of samples comprises the steps of:

extracting a number or numbers of most significant bits from a plurality of samples of the history of samples to produce a plurality of most significant bit sets; and

concatenating bits from the at least one sample and the plurality of most significant bit sets.

23. The method according to claim 21, wherein the history of samples comprise a chronological set of samples having an oldest sample and a newest sample, the at least one sample being neither the oldest sample nor the newest sample.

27. The arrangement according to claim 26, wherein the arrangement comprises a base station in a wireless network.

28. The arrangement according to claim 26, wherein said index builder includes a plurality of storage locations.

29. The arrangement according to claim 28, wherein said index builder further includes a plurality of quantization units, each quantization unit of the plurality of quantization units associated with a respective storage location of the plurality of storage locations, each of the respective storage locations configured to forward a respective sample stored therein.

30. The arrangement according to claim 29, wherein each quantization unit of the plurality of quantization units is configured to forward a respective number of bits of the respective sample stored in the associated respective storage location.

31. The arrangement according to claim 30, wherein the respective number of bits for a first respective sample differs from the respective number of bits for a second respective sample.

32. The arrangement according to claim 30, wherein said index builder further includes a concatenating unit, the concatenating unit being adapted to receive the respective number of bits forwarded from each quantization unit of the plurality of quantization units.

33. The arrangement according to claim 32, wherein the concatenating unit is further adapted to concatenate the received respective number of bits forwarded from each quantization unit of the plurality of quantization units to produce at least a portion of the index value.

34. The arrangement according to claim 33, wherein the concatenating unit is further adapted to concatenate the received respective number of bits forwarded from each quantization unit of the plurality of quantization units and the at least one sample to produce the index value.

35. The arrangement according to claim 28, wherein a first storage location of the plurality of storage locations stores the at least one sample, and a second storage location of the plurality of storage locations stores the at least one of a previous sample and a subsequent sample.

37. The arrangement according to claim 36, wherein the arrangement comprises a node in a telecommunications network.

38. The arrangement according to claim 37, wherein the node comprises a base station, and the telecommunications network comprises a wireless network.

39. The arrangement according to claim 36, wherein the digital output includes at least one sample, and the address is derived responsive to the at least one sample and the frequency of the analog input at a time at which the at least one sample is sampled by said ADC.

17. A method for calibrating analog-to-digital conversion (ADC), comprising the steps of:

converting an analog signal to a digital signal, the digital signal including at least one sample;

producing an index value from the at least one sample and at least one of a previous sample and a subsequent sample;

applying the index value or a derivative thereof to a correction table; and

outputting a corrective calibration value from the correction table responsive to said step of applying the index value or a derivative thereof to a correction table.

24. A system for calibrating analog-to-digital conversion (ADC), comprising:

means for converting an analog signal to a digital signal, the digital signal including at least one sample;

means for producing an index value from the at least one sample and at least one of a previous sample and a subsequent sample;

means for recursively estimating at least one parameter of the analog signal based, at least partly, on the at least one sample;

means for adaptively reconstructing the analog signal in the digital domain based, at least partly, on the at least one parameter;

means for determining whether the reconstruction has converged; and

means for updating a correction table, said means for updating a correction table in operative communication with said means for determining whether the reconstruction has converged, said means for updating a correction table adapted to update the correction table responsive to the index value when the reconstruction has converged.

25. A system for calibrating analog-to-digital conversion (ADC), comprising:

means for converting an analog signal to a digital signal, the digital signal including at least one sample;

means for producing an index value from the at least one sample and at least one of a previous sample and a subsequent sample, said means for producing an index value including means for storing at least a portion of each of the at least one sample and the at least one of a previous sample and a subsequent sample;

means for providing a correction table;

means for applying the index value or a derivative thereof to said means for providing a correction table; and

means for outputting a corrective calibration value from said means for providing a correction table responsive to said means for applying the index value or a derivative thereof to said means for providing a correction table.

26. An arrangement for calibrating analog-to-digital conversion, comprising:

an analog-to-digital converter (ADC), said ADC for converting an analog signal to a digital signal, the digital signal including at least one sample;

an index builder, said index builder receiving the at least one sample, said index builder for building an index value from the at least one sample and at least one of a previous sample and a subsequent sample;

a correction table, said correction table including a plurality of entries; and

a correction table adjuster, said correction table adjuster having access to the index value, said correction table adjuster for altering at least one entry of the plurality of entries, the at least one entry determinable, at least partly, by the index value.

36. An arrangement for calibrating analog-to-digital conversion, comprising:

an analog-to-digital converter (ADC), said ADC for converting an analog input to a digital output, the analog input corresponding to an amplitude and a frequency;

a memory, said memory including a plurality of entries, each entry of the plurality of entries storing an ADC correction value; and

wherein the plurality of entries are organized in said memory in a data structure accessible by an address derived, at least partly, from the amplitude of the analog input and the frequency of the analog input.

40. An arrangement for calibrating analog-to-digital conversion, comprising:

an analog-to-digital converter (ADC), said ADC for converting an analog input to a digital output, the analog input corresponding to a first attribute and a second attribute;

a memory, said memory including a plurality of entries, each entry of the plurality of entries storing an ADC correction value; and

wherein the plurality of entries of said memory are organized in a data structure that is accessible by an address derived responsive to the first attribute of the analog input and the second attribute of the analog input.

41. An arrangement for calibrating analog-to-digital conversion, comprising:

an analog-to-digital converter (ADC), said ADC for converting an analog input to a digital output, the digital output including at least one sample and at least one of a previous sample and a subsequent sample;

a memory, said memory including a plurality of entries, each entry of the plurality of entries storing an ADC correction value; and

wherein the plurality of entries of said memory are stored in a data structure that is addressable responsive to the at least one sample and the at least one of a previous sample and a subsequent sample.

42. An arrangement for calibrating analog-to-digital conversion, comprising:

an analog-to-digital converter (ADC) for receiving an analog input and producing a digital output;

a reconstruction filter for reconstructing the analog input in the digital domain from the digital output;

a first memory for storing a history of the digital output;

a second memory for storing corrective calibration values; and

wherein the history of the digital output is used to access the second memory.

43. The arrangement according to claim 42, wherein the first memory and the second memory comprise a single memory.