Variable clock rate display device

• US 20020093478A1
• Filed: 02/05/2001
• Published: 07/18/2002
• Est. Priority Date: 01/12/2001
• Status: Active Grant

• Current Assignee: Integrated Technology Express
• Original Assignee: Integrated Technology Express
• Inventors: Yeh, Chun Lin
• Granted Patent: US 6,583,785 B2
• Time in Patent Office: Days
• US Class Current: 345/98
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

A variable clock rate device and a method of operating the device. When the display device is first initialized, a pixel clock and a memory read clock are set to the largest values. If the CPU reads from the memory area, the frequency of the pixel clock and the memory read clock is adjusted according to the frequency of the CPU update on-screen memory and the variation of the CPU change on-screen memory block. On the contrary, if the CPU does not initiate any updating, the pixel clock and the memory read clock are tuned down to the smallest possible values to conserve electricity.

Claims

1. A display device having a variable clock rate, comprising:

a decision block for determining the output of the CPU update on-screen mean data and the change on-screen mean area according to a CPU write address signal, an on-screen initial address signal and an on-screen end address signal;

a frequency change block for receiving the CPU update on-screen mean data, the change on-screen mean area, together with a synchronous signal for transmitting a clock set signal;

a first multiplexer for receiving the clock set signal to produce a pixel clock signal output and submitting a corresponding clock set signal;

a second multiplexer for receiving the corresponding clock set signal to produce a memory read clock signal output;

a memory unit for holding data;

a memory controller for receiving the memory read clock signal and reading corresponding data from the memory unit, and then submitting memory read data;

a display controller for receiving the memory read data and the pixel clock signal and generating an on-screen data signal and a corresponding pixel clock signal output; and

a display panel for receiving the on-screen data signal and the corresponding pixel clock signal to produce an image.

2. The device of claim 1, wherein the display panel includes a liquid crystal display (LCD) device.

3. The device of claim 1, wherein the display panel includes a cathode ray tube (CRT).

4. A method of operating a variable clock- rate display device, comprising the steps of:

setting the values of a pixel clock and a memory read clock to the largest possible value on initializing the display device;

adjusting the frequency of the pixel clock and the memory read clock according to the frequency of the CPU update on-screen memory and the variation of the CPU change on-screen memory block if the CPU reads from the memory area; and

adjusting the pixel clock and the memory read clock to the smallest value possible if the CPU performs no update operation.