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Variable clock rate display device

  • US 20020093478A1
  • Filed: 02/05/2001
  • Published: 07/18/2002
  • Est. Priority Date: 01/12/2001
  • Status: Active Grant
First Claim
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1. A display device having a variable clock rate, comprising:

  • a decision block for determining the output of the CPU update on-screen mean data and the change on-screen mean area according to a CPU write address signal, an on-screen initial address signal and an on-screen end address signal;

    a frequency change block for receiving the CPU update on-screen mean data, the change on-screen mean area, together with a synchronous signal for transmitting a clock set signal;

    a first multiplexer for receiving the clock set signal to produce a pixel clock signal output and submitting a corresponding clock set signal;

    a second multiplexer for receiving the corresponding clock set signal to produce a memory read clock signal output;

    a memory unit for holding data;

    a memory controller for receiving the memory read clock signal and reading corresponding data from the memory unit, and then submitting memory read data;

    a display controller for receiving the memory read data and the pixel clock signal and generating an on-screen data signal and a corresponding pixel clock signal output; and

    a display panel for receiving the on-screen data signal and the corresponding pixel clock signal to produce an image.

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