Semiconductor memory device

• US 20020093873A1
• Filed: 03/11/2002
• Published: 07/18/2002
• Est. Priority Date: 10/15/1990
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Toda, Haruki, Saito, Shozo, Tokushige, Kaoru
• Granted Patent: US 6,535,456 B2
• Time in Patent Office: Days
• US Class Current: 365/233.1
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1036 using data shift registers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix: a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the Consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.

Claims

1. A semiconductor memory device, comprising:

a memory cell group comprising a plurality of memory cells arranged in matrix;

specification means for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state;

data input/output (I/O) means for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification means under a control based on a read-out/write-in signal provided from an external section;

count means for counting the number of cycles of a basic clock signal provided from an external section; and

control means for receiving at least one or more specification signals provided from an external section,

for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and

for instructing the count means to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification means and the data I/O operation of the data I/O means, so that the memory access operations for the memory cell group are controlled.

2. A semiconductor memory device according to claim 1, wherein by the control means an address and data of a memory cell first accessed after at least two or more cycles of the basic clock signal counted from the particular cycle.

3. A semiconductor memory device according to claim 1, wherein the control means controls that a row address of the memory cell group is determined after a fixed number of cycles counted from a particular cycle of the basic clock signal obtained by a first specification signal in the specification signals, and a column address of the memory cell is determined after a fixed number of cycles counted from a particular cycle of the basic clock signal obtained by a second specification signal in the specification signals in order to obtain a content of a memory cell addressed by the row address and the column address.

4. A semiconductor memory device, comprising:

a memory cell group comprising a plurality of memory cells grouped into a plurality of cell blocks arranged in matrix;

selection means for outputting a selection signal provided based on a basic clock signal provided consecutively from an external section and an address signal for specifying an address of the cell block in order to select and activate the cell block by interleaving consecutively the memory cell blocks;

specification means for specifying sequentially and activating the memory cells addressed by consecutive addresses in the memory cell block in accordance with the address signal and the selection signal for activating and enterring the cell block in an active state by the selection means;

data input/output (I/O) means for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification means under a control based on a read-out/write-in signal provided from an external section;

count means for counting the number of cycles of the basic clack signal provided from an external-section; and

control means for receiving at least one or more specification signals provided from an external section,

for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and

for instructing the count means to count the number of counts of the basic clock signal based on the control signal, and for controlling a selection and activation operation executed by the selection means, a specification operation executed by the specification means and the data I/O operation executed by the data I/O means, so that the memory access operations for the memory cell group are controlled.

5. A semiconductor memory device according to claim 4, wherein under the control of the control means a fetch operation for data in x-th memory cell block (x=i−

m (mod n), modulus n) is started before m cycles from a cycle of the basic clock signal counted from a starting cycle to access the i-th memory cell block and outputs the content of the x-th memory cell block when consecutive data are fetched from the n (n≧

2) memory cell blocks.

6. A semiconductor memory device according to claim 4, wherein

the memory cell group consists of small groups of n memory cell blocks,

the k (n>

k) memory cell blocks make up of a large memory cell block, the N (n>

k>

N) large memory cell blocks make up of the small memory cell group (n=k×

N),

a column decoder is provided every large memory cell block,

the k memory cell blocks in each large memory cell block are controlled by the same column decoder,

each column decoder is activated every n-th cycle of the basic clock signal for specifying consecutively the memory cells in the k memory cell blocks under the control of the specification means, and

each of the N column decoders can keep a specification for the large memory cell block specified during at least 2k cycles of the basic clock signal.

7. A semiconductor memory device according to claim 4, wherein the selection means provides a plurality of internal basic clock signals, which are only different in phase, from the basic clock signal, the plurality of the memory cell blocks are selected and activated by interleaving consecutively them in a fixed order by using the internal basic clock signals and a part of an address signal for specifying a head memory cell block to be accessed, in spite of the state of the internal basic clock signal at which the memory cell block is accessed first by the internal basic clock signal.

8. A semiconductor memory device, comprising:

a memory cell group comprising a plurality of memory cells arranged in matrix;

specification means for specifying and activating at once a fixed number of the memory cells, as a package memory cell, addressed by consecutive addresses in the memory cells in accordance with a basic clock signal and an address signal provided from an external section;

store means for storing temporarily data from or to the fixed number of the memory cells specified at the same time by the specification means;

control means for carrying out at once a data transfer operation between the fixed number of the memory cells specified by the specification means and the store means in accordance with the basic clock signal and the specification signal;

data input/output (I/O) means for executing sequentially a data read-out/write-in operation (data I/O operation) for the store means in accordance with the basic clock signal; and

count means for counting the number of cycles of a basic clock signal,

wherein the control means receives at least one or more specification signals provided from an external section,

outputs a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal,

instructs the count means to count the number of counts of the basic clock signal based on the control signal,

controls a specification operation executed by the specification means and the data I/O operation of the data I/O means based on the number of the cycles including the number of the cycles at least two or more counted from the particular cycle by the count means, and

so that the control means controls the memory access operations for the memory cell group.

9. A semiconductor memory device according to claim 8, wherein the store means comprises a plurality of parts, each having same construction and stores data in the fixed number of the memory cells, and

the control means controls that during data is transferred between one part in the store means and an external section in accordance with the basic clock signal, data is transferred between the memory cell group and the other part in the store means.

10. A semiconductor memory device according to claim 8, wherein the store means comprises a plurality of registers and a plurality of gates, the number of gates is equal to the number of the registers, the registers store all data in the fixed number of the memory cells, and each gate is capable of switching whether or not data in the register is transferred to the memory cell when all data in the store means are transferred at once into the memory cell group.