Electronic component with stacked semiconductor chips and method of producing the component

• US 20020094607A1
• Filed: 01/16/2002
• Published: 07/18/2002
• Est. Priority Date: 01/16/2001
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Wennemuth, Ingo, Gebauer, Uta
• Granted Patent: US 6,686,648 B2
• Time in Patent Office: Days
• US Class Current: 438/114
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The electronic component has semiconductor chips that are stacked on one another. On their active top sides, the chips having interconnects for rewiring to contact areas through contacts formed on the sawn edges of the semiconductor chip. The electronic components of overlying and underlying semiconductor chips are thus connected to one another via the through contacts.

Claims

1. An electronic component, comprising:

a stack of a plurality of semiconductor chips each having an active top side and a sawn edge;

contact areas and interconnects formed on said active top side for rewiring to contact areas of respectively adjacent semiconductor chips; and

said interconnects connecting to said contact areas on said active top side, extending toward said sawn edge of said semiconductor chip, and connecting to said respectively adjacent semiconductor chips via through-contacts formed at said sawn edge of said semiconductor chip.

2. The electronic component according to claim 1, wherein said stack of semiconductor chips includes a bottommost semiconductor chip formed with solder deposits in place of said through contacts.

3. The electronic component according to claim 2, wherein said solder deposit on said bottommost semiconductor chip is formed with a screen-printing solder deposit.

4. The electronic component according to claim 2, which comprises a rewiring plane in each case arranged between said semiconductor chips.

5. The electronic component according to claim 1, wherein said through contacts include an adhesion promoter layer on an inner wall thereof.

6. The electronic component according to claim 5, wherein said adhesion promoter layer includes a material selected from the group consisting of titanium and titanium alloy.

7. The electronic component according to claim 1, wherein said through contacts are formed with a solderable surface coating.

8. The electronic component according to claim 1, wherein said through contacts are formed with a surface coating made of a material selected from the group consisting of copper, silver, gold, and alloys thereof.

9. The electronic component according to claim 1, which comprises an insulating layer disposed between said active semiconductor top side and said interconnects for rewiring.

10. The electronic component according to claim 9, wherein said insulating layer includes a polymer.

11. The electronic component according to claim 9, wherein said insulating layer is a polyimide layer.

12. The electronic component according to claim 1, wherein said through contacts are circular arcs in cross section.

13. The electronic component according to claim 1, wherein said semiconductor chips include memory chips.

15. The method according to claim 14, wherein the step of forming the through contact holes comprises reactive ion beam etching.

16. The method according to claim 14, wherein the step of forming the through contact holes comprises laser beam vaporization.

17. The method according to claim 14, wherein the step of forming the through contact holes comprises electrolytic cannula etching.

18. The method according to claim 14, which comprises coating the inner walls of the through contact holes with an adhesion promoter selected from the group consisting of titanium and a titanium alloy.

19. The method according to claim 14, which comprises coating the inner walls of the through contact holes with a solderable surface coating selected from the group consisting of copper, silver, gold, and alloys thereof.

20. The method according to claim 14, which comprises coating the inner walls of the through contact holes with a vapor deposition process.

21. The method according to claim 20, which comprises coating the inner walls of the through contact holes with a vapor deposition process selected from the group consisting of chemical vapor deposition and physical vapor deposition.

22. The method according to claim 14, which comprises electroplating the inner walls of the through contact holes.

23. The method according to claim 14, which comprises screen printing the interconnects for rewiring on the patterned insulating layer.

24. The method according to claim 14, which comprises forming a wafer with semiconductor chips to be used as bottommost semiconductor chips of a stack, and forming solder deposits instead of through contacts on the semiconductor wafer of the bottommost semiconductor chips.

25. The method according to claim 14, which comprises stacking a plurality of semiconductor wafers on one another, connecting the through contacts to the interconnects of respectively overlying or underlying semiconductor wafers, and subsequently separating the stacked semiconductor wafers to form stacks of semiconductor chips.

26. The method according to claim 25, wherein the connecting step comprises heating the stacked semiconductor wafers to a soldering temperature.

14. A method of fabricating an electronic component having semiconductor chips stacked on one another and connected via rewiring planes and through contacts formed at sawn edges of the semiconductor chip, the method which comprises the following steps:

providing a semiconductor wafer with semiconductor chips arranged in rows and columns and sawing track regions therebetween;

applying an insulating layer for protection and for insulation of an active top side of the semiconductor chips;

forming through contact holes in the sawing track regions, the contact holes having a diameter greater than a width of a saw blade for dicing the semiconductor wafer;

coating an inner wall of the through contact holes with at least one of an adhesion promoter and a solderable surface coating;

filling the through contact holes with solder material to form through contacts;

patterning the insulating layer by uncovering contact areas on the active top side of the semiconductor chip and applying interconnects for rewiring on the insulating layer, the interconnects for rewiring connecting individual contact areas to the through contacts;

dicing the semiconductor wafer to form semiconductor chips; and

stacking a plurality of semiconductor chips to form an electronic component.