Arithmetic unit comprising a memory shared by a plurality of processors
First Claim
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1. An arithmetic unit comprising:
- a first arithmetic processing part for carrying out arithmetic processing; and
a memory part shared by said first arithmetic processing part and a second arithmetic processing part which allows arithmetic processing to be carried out independently of said first arithmetic processing part, said memory part includes first and second buffer parts allowing implementation of data write in and data read out independently of each other and an access control part for determining pairs of each of said first and second buffer parts and one of said first or second arithmetic processing parts based on a buffer designation that can be changed by said second arithmetic part, and for carrying out exclusive access in each of said pairs.
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Abstract
A shared memory shared between a parent processor and a coprocessor core includes two buffers. An access control part allows one of the two buffers to exclusively access one of either the parent processor or the coprocessor core in accordance with the buffer designation data. The buffer designation data are stored in a control register allocated to a specific address and are rewritten by the parent processor in a software manner.
90 Citations
20 Claims
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1. An arithmetic unit comprising:
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a first arithmetic processing part for carrying out arithmetic processing; and
a memory part shared by said first arithmetic processing part and a second arithmetic processing part which allows arithmetic processing to be carried out independently of said first arithmetic processing part, said memory part includes first and second buffer parts allowing implementation of data write in and data read out independently of each other and an access control part for determining pairs of each of said first and second buffer parts and one of said first or second arithmetic processing parts based on a buffer designation that can be changed by said second arithmetic part, and for carrying out exclusive access in each of said pairs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An arithmetic unit comprising:
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a first arithmetic processing part for carrying out arithmetic processing; and
a memory part shared by said first arithmetic processing part and a second arithmetic processing part which allows arithmetic processing to be carried out independently of said first arithmetic processing part, said memory part including first and second buffer parts, which allow data write in and data read out independent of each other and each of which having two input/output ports, and an access control part which transmits read out data from one of said first and second buffer parts, which is designated in accordance with a first read buffer designation that can be changed by said second arithmetic processing part, to said first arithmetic processing part and which transmits read out data from one of said first and second buffer parts, which is designated in accordance with a second read buffer designation that can be changed by said second arithmetic processing part, to said second arithmetic processing part, in the case that a data read out request is received from, at least, one of said first and second arithmetic processing parts, said access control part transmitting write in data from one of said first and second arithmetic processing parts to one of said first and second buffer parts which is determined based on a write buffer designation that can be changed by said second arithmetic processing part in the case that a data write in request is received from the above specified first or second arithmetic processing part. - View Dependent Claims (12, 13, 14, 16, 17, 18, 19, 20)
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15. An arithmetic unit comprising:
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a first arithmetic processing part for carrying out arithmetic processing; and
a memory part shared by said first arithmetic processing part and a second arithmetic processing part which allows arithmetic processing to be carried out independently said first arithmetic processing part, wherein said memory part includes a plurality of buffer parts, allowing implementation of data write in and data read out to be carried out independent of each other, and an access control part which carries out access between one of said plurality of buffers which is determined based on a first buffer designation that can be changed by said second arithmetic processing part and said first arithmetic processing part as well as access between one of said plurality of buffers which is determined based on a second buffer designation that can be changed by said second arithmetic processing part and said second arithmetic processing part.
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Specification