Multiprocessor apparatus

• US 20020095609A1
• Filed: 07/02/2001
• Published: 07/18/2002
• Est. Priority Date: 01/15/2001
• Status: Abandoned Application

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tokunaga, Yuichi
• Application Number:
  US09/895,151
• Publication Number:
  US 20020095609A1
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/4054 where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multiprocessor apparatus includes a high speed processor coupled to a high speed bus, a low speed processor coupled to a low speed bus, a bus adapter for coupling between the high speed bus and the low speed bus, an operating system for determining as to at which processor application program is to be executed, and an activation controller for activating clock signal for the processor which executes the application program, based on the determination result of the operating system.

Claims

1. A multiprocessor apparatus comprising:

a high speed processor operating at a high speed;

a low speed processor operating at a low speed; and

an activation controller for controlling activation and inactivation of each of said high speed processor and said low speed processor based on application program to be processed.

2. The multiprocessor apparatus according to claim 1, further comprising a processing determining unit for determining as to at which of said processors application program is to be processed, wherein said activation controller controls activation and inactivation of each of said high speed processor and said low speed processor based on a determination result of said processing determining unit.

3. The multiprocessor apparatus according to claim 1, further comprising a bus coupling unit which couples a high speed bus for coupling said high speed processor and a low speed bus for coupling said low speed processor, wherein said bus coupling unit includes a switch coupled to a memory, for switching connection and disconnection between said memory and said high speed bus.

4. The multiprocessor apparatus according to claim 1, further comprising:

a memory coupled to said high speed bus for storing data and program required for said high speed processor to process said application program; and

a memory coupled to said low speed bus for storing data and program required for said low speed processor to process said application program.

5. The multiprocessor apparatus according to claim 4, further comprising a memory which stores data and program necessary for transferring said data and program required for said low speed processor to process said application program from said memory coupled to said high speed bus to said memory coupled to said low speed bus.

6. The multiprocessor apparatus according to claim 4, further comprising a DMA circuit for transferring said data and program required for said low speed processor to process said application program from said memory coupled to said high speed bus to said memory coupled to said low speed bus.

7. The multiprocessor apparatus according to claim 4, wherein said low speed processor transfers said data and program required for said low speed processor to process said application program from said memory coupled to said high speed bus.

8. The multiprocessor apparatus according to claim 1, wherein said activation controller includes a clock switch for activating and stopping clock signals for said respective processors.

9. The multiprocessor apparatus according to claim 1, wherein said activation controller includes a poser source switching for activating and stopping power sources for said respective processors.

10. The multiprocessor apparatus according to claim 1, wherein said low speed processor has minimum function required for processing said application program at a low speed.

11. The multiprocessor apparatus according to claim 1, wherein said low speed processor is set in a manner that operation voltage thereof is set to a low value and a frequency of a clock signal supplied thereto is set to a small value.

12. The multiprocessor apparatus according to claim 3, wherein said bus coupling unit includes a register, and said bus coupling unit changes contents of said register based on a result of determination of said processing determining unit, and said activation controller controls an activation state of said processor based on contents of said register.

13. The multiprocessor apparatus according to claim 1, wherein said low speed processor requires said activation controller to make said low speed processor inactivate after completion of processing of said application program.