Compiler and register allocation method
First Claim
1. A compiler, which converts into a machine language the source code of a program written in a programming language and optimizes said program, comprising:
- a DAG analysis unit for constructing and analyzing a DAG for an instruction in a program to be processed;
an interference graph construction unit for employing the analysis results obtained by said DAG analysis unit to construct an interference graph representing the probability that an interference will occur between variables used by said instruction; and
a graph identifier for allocating registers for said instruction based on said interference graph that is constructed by said interference graph construction unit, wherein, when the overall time for executing said program is extended unless predetermined multiple instructions are executed in parallel, said interference graph construction unit assumes that an interference has occurred among variables used by said multiple instructions, and constructs said interference graph.
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Accused Products
Abstract
The number of interferences between variables during graph coloring is reduced, while maintaining the possibility that the instructions will be executed in parallel, so that an efficient compiler can be provided. A compiler, which converts into a machine language the source code of a program written in a programming language and optimizes the program, includes: a DAG analysis unit 11 for constructing and analyzing a DAG for an instruction in a program to be processed; an interference graph construction unit 12 for employing the analysis results to construct an interference graph representing the probability that an interference will occur between variables used by the instruction; and a graph coloring unit 13 for allocating registers for the instruction based on the interference graph that is constructed, wherein, when the overall time for executing the program is extended unless predetermined multiple instructions are executed in parallel, the interference graph construction unit 12 assumes that an interference has occurred among variables used by the multiple instructions, and constructs the interference graph.
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Citations
15 Claims
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1. A compiler, which converts into a machine language the source code of a program written in a programming language and optimizes said program, comprising:
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a DAG analysis unit for constructing and analyzing a DAG for an instruction in a program to be processed;
an interference graph construction unit for employing the analysis results obtained by said DAG analysis unit to construct an interference graph representing the probability that an interference will occur between variables used by said instruction; and
a graph identifier for allocating registers for said instruction based on said interference graph that is constructed by said interference graph construction unit, wherein, when the overall time for executing said program is extended unless predetermined multiple instructions are executed in parallel, said interference graph construction unit assumes that an interference has occurred among variables used by said multiple instructions, and constructs said interference graph. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A computer that includes a compiler, for compiling source code for an input program, comprising:
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a DAG analysis unit, for constructing and analyzing a DAG for an instruction extracted from said program;
an interference graph construction unit, for employing the analysis results obtained by said DAG analysis unit to construct, with the condition that the overall execution time of said program will not be extended, an interference graph that is required to ensure the parallel execution of said program and that represents interferences between variables used by instructions in said program; and
a register allocation unit for allocating registers to said instruction based on said interference graph that is prepared by said interference graph construction unit. - View Dependent Claims (8)
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9. A register allocation method, which for the performance of optimization to improve programming efficiency employs graph coloring to allocate registers to instructions in a program, comprising the steps of:
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constructing and analyzing a DAG for said instructions based on said program;
employing as a reference the longest non-parallel instruction queue in said DAG, and constructing an interference graph assumes that an interference has occurred among variables used by said multiple instructions, based on the DAG analysis results, when said instruction queue is extended, unless predetermined multiple instructions are executed in parallel; and
allocating registers for said instructions based on said obtained interference graph. - View Dependent Claims (10, 11, 12, 13)
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14. A storage medium on which input means of a computer stores a computer-readable program, which permits said computer to perform:
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a process for constructing and analyzing a DAG for said instructions based on said program;
a process for employing as a reference the longest non-parallel instruction queue in said DAG, and constructing an interference graph assumes that an interference has occurred among variables used by said multiple instructions, based on the DAG analysis results, when said instruction queue is extended, unless predetermined multiple instructions are executed in parallel; and
a process for allocating registers for said instructions based on said obtained interference graph.
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15. A program transmission apparatus comprising:
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storage means for storing a program for permitting a computer to perform a process for constructing and analyzing a DAG for said instructions based on said program, a process for employing as a reference the longest non-parallel instruction queue in said DAG, and constructing an interference graph assumes that an interference has occurred among variables used by said multiple instructions, based on the DAG analysis results, when said instruction queue is extended, unless predetermined multiple instructions are executed in parallel, and a process for allocating registers for said instructions based on said obtained interference graph; and
transmission means for reading said program from said storage means and transmitting said program.
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Specification