Circuit board

• US 20020096357A1
• Filed: 01/24/2001
• Published: 07/25/2002
• Est. Priority Date: 01/25/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Iwasaki, Shota, Inaba, Takehito
• Granted Patent: US 6,815,619 B2
• Time in Patent Office: Days
• US Class Current: 174/250
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0218 by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence

Abstract

A circuit board including a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, and a dielectric layer covering a part of the interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the interconnect layer and the edge of the electrically-floating conductive layer. In accordance with the present invention, almost all the surface of the base member is covered with the interconnect layer and the floating conductive layer disposed parallel to each other on a substantially single plane In the circuit board, the moisture does not enter into the rear surface of the dielectric layer through the externally exposed portion to improve the packaging rank.

Claims

1. A circuit board comprising a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, and a dielectric layer covering a part of the interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the interconnect layer and the edge of the electrically-floating conductive layer.

2. The circuit board as defined in claim 1, wherein a pair of the interconnect layers are disposed on each of both surfaces of the base member.

3. The circuit board as defined in claim 2, wherein volumes of the pair of the interconnect layers are substantially same.

4. The circuit board as defined in claim 1, wherein the interconnect layer includes patterns having a larger width.

5. A circuit board comprising a base member, an first interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the first interconnect layer, and a dielectric layer covering a part of the first interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the first interconnect layer and the edge of the electrically-floating conductive layer, and a second interconnect layer formed on the dielectric layer.

6. The circuit board as defined in claim 5, wherein the interconnect layer includes patterns having a larger width.

7. A circuit board comprising a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, a dielectric layer covering a part of the interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the interconnect layer and the edge of the electrically-floating conductive layer, and a die disposed on the dielectric layer.

8. The circuit board as defined in claim 7, wherein the interconnect layer includes patterns having a larger width.