Low voltage dual-well trench MOS device

• US 20020096714A1
• Filed: 01/22/2001
• Published: 07/25/2002
• Est. Priority Date: 01/22/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Wheatley, Carl Franklin Jr., Zeng, Jun
• Granted Patent: US 6,552,391 B2
• Time in Patent Office: Days
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An improved low-voltage MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery characteristics comprises a semiconductor substrate on which is disposed a doped upper layer of a first conduction type. The upper layer includes a doped first well region of the first conduction type and a doped well region of the second conduction type underlying the first well region. The upper layer further includes at its upper surface a heavily doped source region of the first conduction type and a heavily doped body region of a second and opposite conduction type. A trench gate comprising a conductive material separated from the upper layer by an insulating layer is disposed in the upper layer of the substrate.

Claims

1. An improved low-voltage MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery characteristics, said device comprising:

a semiconductor substrate;

a lightly doped upper layer of a first conduction type disposed on said substrate and comprising a doped first well region of said first conduction type and a doped second well region of a second conduction type, said first well region underlying said second well region;

said upper layer further comprising a heavily doped source region of said first conduction type and a heavily doped body region of a second and opposite conduction type disposed at an upper surface of said upper layer; and

a trench gate disposed in said upper layer and comprising a conductive material separated from said upper layer by an insulating layer.

2. The MOS device of claim 1 wherein said doped upper layer comprises an epitaxial layer.

3. The MOS device of claim 1 wherein said first conduction type is N and said second conduction type is P.

4. The MOS device of claim 1 wherein said substrate comprises monocrystalline silicon and said insulating layer comprises silicon dioxide.

5. The MOS device of claim 1 wherein said conductive material included in said gate comprises highly doped polysilicon.

6. The MOS device of claim 1 wherein said conductive material in said gate trench is recessed, having an upper surface that is lower than said upper surface of said upper layer of said substrate.

7. The MOS device of claim 1 further comprising a highly doped JFET region underlying said gate trench and merging with said first well region.

8. The MOS device of claim 1 further comprising an interlevel dielectric layer overlying said trench gate and a source metal contact.

9. The MOS device of claim 8 wherein said interlevel dielectric layer further overlies a portion of said source region.

10. An improved low-voltage MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery characteristics, said device comprising:

a semiconductor substrate comprising a lightly doped upper layer having an upper surface, said upper layer being of a first conduction type;

a trench gate disposed in said upper layer and comprising a conductive material separated from said upper layer by an insulating layer, said conductive material having an upper surface that is lower than said upper surface of said upper layer;

a doped first well region of said first conduction type and a doped second well region of a second conduction type disposed in said upper layer said first well region underlying said second well region and merging with a highly doped JFET region underlying said trench gate;

a heavily doped source region of said first conduction type and a heavily doped body region of a second and opposite conduction type disposed at said upper surface of said upper layer;

an interlevel dielectric layer overlying said trench gate; and

a source metal contact.

11. The MOS device of claim 10 wherein said interlevel dielectric layer further overlies a portion of said source region.

12. The MOS device of claim 10 wherein said doped upper layer comprises an epitaxial layer.

13. The MOS device of claim 10 wherein said first conduction type is N and said second conduction type is P.

14. The MOS device of claim 10 wherein said substrate comprises monocrystalline silicon and said insulating layer comprises silicon dioxide.

15. The MOS device of claim 10 wherein said conductive material included in said gate comprises highly doped polysilicon.

16. The MOS device of claim 10 wherein said interlevel dielectric layer comprises borophosphosilicate glass (BPSG).