Semiconductor device

• US 20020096715A1
• Filed: 01/25/2002
• Published: 07/25/2002
• Est. Priority Date: 01/25/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Yamada, Manabu, Shimomura, Akihiro, Sumida, Wataru, Maruoka, Michiaki
• Granted Patent: US 6,639,278 B2
• Time in Patent Office: Days
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

At one of main surfaces of a silicon substrate serving as an N+type drain region is arranged an N type first high resistance drift layer. On the first high resistance drift layer is arranged an N−type second high resistance drift layer. A P− type high resistance buried layer is arranged on the surface layer of the first high resistance drift layer and the bottom layer of the second high resistance drift layer at a position right under each of a plurality of P type base regions arranged on the surface layer of the second high resistance drift layer. The thickness T1 of the first high resistance drift layer is set in such a manner that a depletion layer extending over the first high resistance drift layer reaches through the drain region at a voltage lower than a sharing voltage V1 shared by the first high resistance drift layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate serving as a drain region of one conductive type;

a first high resistance drift layer of one conductive type provided on a surface of said semiconductor substrate;

second to (n+1)th high resistance drift layers of one conductive type provided on said first high resistance drift layer (wherein n is an integer of 1 or more);

a base region of other conductive type provided on a surface layer of said (n+1)th high resistance drift layer;

a source region of one conductive type provided on a surface layer of said base region;

a first high resistance buried layer of other conductive type provided on a surface layer of said first high resistance drift layer and a bottom layer of said second high resistance drift layer at a position right under said base region;

second to nth high resistance buried layers of other conductive type respectively provided on surface layers of said second to nth high resistance drift layers and bottom layers of said third to (n+1)th high resistance drift layers at a position right under said base region;

a gate electrode provided on said base region held between said (n+1)th high resistance drift layer and said source region via a gate oxide film;

a source electrode in ohmic contact with said source region over said base region and said source region; and

a drain electrode provided on the other surface of said semiconductor substrate;

wherein thickness of said first high resistance drift layer being established in such a manner that a depletion layer formed within said first high resistance drift layer reaches through said drain region, when a voltage lower than a sharing voltage shared by said first high resistance drift layer out of a predetermined withstand voltage between said source electrode and said drain electrode is applied to a PN junction between said first high resistance buried layer and said first high resistance drift layer.

3. The semiconductor device according to claim 1, wherein said thickness of said first high resistance drift layer is established in such a manner that an ON resistance becomes minimum at a predetermined withstand voltage of said semiconductor device by using a graph in which variables thereof are an ON resistance, a withstand voltage and a thickness of said first high resistance drift layer of said semiconductor device.

4. The semiconductor device according to claim 1, wherein said thickness of said first high resistance drift layer is established in such a manner that said withstand voltage of said semiconductor device becomes maximum by using a graph in which variables thereof are an ON resistance, a withstand voltage and a thickness of said first high resistance drift layer of said semiconductor device.

5. The semiconductor device according to claim 4, wherein an impurity concentration of said first high resistance drift layer is an impurity concentration at a maximum withstand voltage of said semiconductor device.

6. The semiconductor device according to claim 1, wherein said thickness of said first high resistance drift layer is smaller than that of each of said second to (n+1)th high resistance drift layers.

7. The semiconductor device according to claim 1, further comprising:

a plurality of guard ring layers of other conductive type provided on a surface layer of said (n+1)th high resistance drift layer so as to surround said plurality of base regions;

a plurality of first buried guard ring layers of other conductive type provided on said surface layer of said first high resistance drift layer and said bottom layer of said second high resistance drift layer under said guard ring layer so as to surround said first high resistance buried layer; and

a plurality of second to nth buried guard ring layers of other conductive type provided on surface layers of said second to nth high resistance drift layers and bottom layers of said third to (n+1)th high resistance drift layers under said guard ring layer so as to respectively surround said second to nth high resistance buried layers.

2. A semiconductor device comprising:

a semiconductor substrate serving as a drain region of one conductive type;

a first high resistance drift layer of one conductive type provided on a surface of said semiconductor substrate;

a second high resistance drift layers of one conductive type provided on said first high resistance drift layer;

a base region of other conductive type provided on a surface layer of said second resistance drift layer;

a source region of one conductive type provided on a surface layer of said base region;

a first high resistance buried layer of other conductive type provided on a surface layer of said first high resistance drift layer and a bottom layer of said second high resistance drift layer at a position right under said base region;

a gate electrode provided on said base region held between said second high resistance drift layer and said source region via a gate oxide film;

a source electrode in ohmic contact with said source region over said base region and said source region; and

a drain electrode provided on the other surface of said semiconductor substrate;

wherein thickness of said first high resistance drift layer being established in such a manner that a depletion layer formed within said first high resistance drift layer reaches through said drain region, when a voltage lower than a sharing voltage shared by said first high resistance drift layer out of a predetermined withstand voltage between said source electrode and said drain electrode is applied to a PN junction between said first high resistance buried layer and said first high resistance drift layer.

8. A semiconductor device comprising:

a semiconductor substrate serving as a drain region of one conductive type;

a first high resistance drift layer of one conductive type provided on a surface of said semiconductor substrate;

second to (n+1)th high resistance drift layers of one conductive type provided on said first high resistance drift layer (wherein n is an integer of 1 or more);

a base region of other conductive type provided on a surface layer of said (n+1)th high resistance drift layer;

a source region of one conductive type provided on a surface layer of said base region;

a first high resistance buried layer of other conductive type provided on a surface layer of said first high resistance drift layer and a bottom layer of said second high resistance drift layer at a position right under said base region;

second to nth high resistance buried layers of other conductive type respectively provided on surface layers of said second to nth high resistance drift layers and bottom layers of said third to (n+1)th high resistance drift layers at a position right under said base region;

a trench provided on a surface of said (n+1)th high resistance drift layer so as to penetrate said source region and base region;

a gate oxide film formed on an inner surface of said trench;

a gate electrode disposed within said trench;

a source electrode in ohmic contact with said source region over said base region and said source region; and

a drain electrode provided on the other surface of said semiconductor substrate;

wherein thickness of said first high resistance drift layer being established in such a manner that a depletion layer formed within said first high resistance drift layer reaches through said drain region, when a voltage lower than a sharing voltage shared by said first high resistance drift layer out of a predetermined withstand voltage between said source electrode and said drain electrode is applied to a PN junction between said first high resistance buried layer and said first high resistance drift layer.

9. A semiconductor device comprising:

a semiconductor substrate serving as a drain region of one conductive type;

a first high resistance drift layer of one conductive type provided on a surface of said semiconductor substrate;

a second high resistance drift layers of one conductive type provided on said first high resistance drift layer;

a base region of other conductive type provided on a surface layer of said second resistance drift layer;

a source region of one conductive type provided on a surface layer of said base region;

a first high resistance buried layer of other conductive type provided on a surface layer of said first high resistance drift layer and a bottom layer of said second high resistance drift layer at a position right under said base region;

a trench provided on a surface of said second high resistance drift layer so as to penetrate said source region and base region;

a gate oxide film formed on an inner surface of said trench;

a gate electrode disposed within said trench;

a source electrode in ohmic contact with said source region over said base region and said source region; and

a drain electrode provided on the other surface of said semiconductor substrate;

wherein thickness of said first high resistance drift layer being established in such a manner that a depletion layer formed within said first high resistance drift layer reaches through said drain region, when a voltage lower than a sharing voltage shared by said first high resistance drift layer out of a predetermined withstand voltage between said source electrode and said drain electrode is applied to a PN junction between said first high resistance buried layer and said first high resistance drift layer.