Structure and method of MOS transistor having increased substrate resistance
First Claim
1. An integrated circuit fabricated in a semiconductor of a first conductivity type, said circuit having at the surface at least one lateral MOS transistor comprising:
- a source and a drain, each having at said surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and
a semiconductor region within said semiconductor of said first conductivity type, having a resistivity higher than the remainder of said semiconductor, said region extending vertically below said transistor while laterally limited to the area of the transistor such that the resistivity under said gate is different from the resistivity under said source and drain regions.
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Abstract
Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.
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Citations
33 Claims
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1. An integrated circuit fabricated in a semiconductor of a first conductivity type, said circuit having at the surface at least one lateral MOS transistor comprising:
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a source and a drain, each having at said surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and
a semiconductor region within said semiconductor of said first conductivity type, having a resistivity higher than the remainder of said semiconductor, said region extending vertically below said transistor while laterally limited to the area of the transistor such that the resistivity under said gate is different from the resistivity under said source and drain regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 16, 17, 18, 19, 20, 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 33)
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12. An integrated circuit fabricated in a semiconductor of a first conductivity type, said circuit having at the surface at least one lateral MOS transistor comprising:
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a source and a drain, each having at said surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and
a semiconductor region within said semiconductor of said first conductivity type, having a resistivity higher than the remainder of said semiconductor, said region extending vertically below said transistor while laterally limited to the area of the transistor, and embedded in said region a volume of said opposite conductivity type, said volume thereby further impeding the flow of substrate current from said transistor.
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14. A method of increasing the p-type semiconductor resistivity under the active area of a high-voltage NMOS transistor having a gate, comprising the steps of:
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depositing a photoresist layer over said transistor and opening a window in said layer over said active area of said transistor; and
implanting, at high energy, n-doping ions into said p-type semiconductor through said window, creating a deep region having a net p-type doping lower than that of said p-type semiconductor remote from said transistor active area.
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15. A method of fabricating an NMOS transistor in the surface of an integrated circuit, said transistor having increased substrate resistance in the p-type semiconductor of said integrated circuit, comprising the steps of:
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forming non-conductive electrical isolation regions into said p-type semiconductor for defining the lateral boundaries of the NMOS transistor active area;
implanting p-doping or n-doping ions to adjust the background doping level of said p-type semiconductor;
depositing over said surface a layer of insulating material suitable as gate dielectric, covering said transistor area;
depositing a layer of poly-silicon or other conductive material onto said insulating layer;
protecting a portion of said poly-silicon and etching the remainder thereof, defining the gate area of said transistor;
depositing a first photoresist layer and opening a window therein, exposing the surface of said area between said isolation regions;
implanting, at low energy, n-doping ions into said exposed surface area, creating shallow n-doped layers under said surface, suitable as extended source and drain of said transistor;
implanting, at high energy, n-doping ions into said exposed surface area, creating a deep region under said surface having a net p-type doping lower than that of said p-type semiconductor remote from said transistor active area;
removing said first photoresist layer;
depositing conformal insulating layers of an insulator, such as silicon nitride or silicon dioxide, over said surface and directional plasma etching said insulating layers so that only side walls around the poly-silicon gate remain;
depositing a second photoresist layer and opening a window therein, exposing the surface of said area between said isolation regions;
implanting, at medium energy, n-doping ions into said exposed surface area, creating an n-doped region that extends to a medium depth under said surface, suitable as deep source and drain of said transistor; and
removing said second photoresist layer.
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25. A method of increasing the n-type semiconductor resistivity under the active area of a high-voltage PMOS transistor having a gate, comprising the steps of:
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depositing a photoresist layer over said transistor and opening a window in said layer over said active area of said transistor; and
implanting, at high energy, p-doping ions into said n-type semiconductor through said window, creating a deep region having a net n-type doping lower than that of said n-type semiconductor remote from said transistor active area.
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26. A method of fabricating a PMOS transistor in the surface of an integrated circuit, said transistor having increased substrate resistance in the n-type semiconductor of an integrated circuit, comprising the steps of:
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forming non-conductive electrical isolation regions into said n-type semiconductor for defining the lateral boundaries of the PMOS transistor active area;
implanting n-doping or p-doping ions to adjust the background doping level of said n-type semiconductor;
depositing over said surface a layer of insulating material suitable as gate dielectric, covering said transistor area;
depositing a layer of poly-silicon or other conductive material onto said insulating layer;
protecting a portion of said poly-silicon and etching the remainder thereof, defining the gate area of said transistor;
depositing a first photoresist layer and opening a window therein, exposing the surface of said area between said isolation regions;
implanting, at low energy, p-doping ions into said exposed surface area, creating shallow p-doped layers under said surface, suitable as extended source and drain of said transistor;
implanting, at high energy, p-doping ions into said exposed surface area, creating a deep region under said surface having a net n-type doping lower than that of said n-type semiconductor remote from said transistor active area;
removing said first photoresist layer;
depositing conformal insulating layers of an insulator, such as silicon nitride or silicon dioxide, over said surface and directional plasma etching said insulating layers so that only side walls around the poly-silicon gate remain;
depositing a second photoresist layer and opening a window therein, exposing the surface of said area between said insulation regions;
implanting, at medium energy, p-doping ions into said exposed surface area, creating an p-doped region that extends to a medium depth under said surface, suitable as deep source and drain of said transistor; and
removing said second photoresist layer.
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Specification