Transient frequency in dynamic threshold metal-oxide-semiconductor field effect transistors

• US 20020096723A1
• Filed: 12/07/2000
• Published: 07/25/2002
• Est. Priority Date: 12/31/1999
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Awaka, Kaoru
• Application Number:
  US09/732,249
• Publication Number:
  US 20020096723A1
• Time in Patent Office: Days
• US Class Current: 257/360
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit having a primary transistor (12, 22, 32, 42, 52) and an associated secondary transistor (15, 25, 35, 45, 55) for dynamically varying the voltage of the body node (B) of the primary transistor (12, 22, 32, 42, 52) responsive to the gate voltage of the primary transistor (12, 22, 32, 42, 52) is disclosed. According to the disclosed embodiments of the invention, each of the primary transistor (12, 22, 32, 42, 52) and secondary transistor (15, 25, 35, 45, 55) are bulk transistors, formed at a surface of a substrate (11), where the secondary transistor (15, 25, 35, 45, 55) has a much smaller channel width than that of the primary transistor (12, 22, 32, 42, 52), to enhance the transient frequency of the device. In each case, the secondary transistor (15, 25, 35, 45, 55) has its source-drain path connected between the gate (G) and the body node (B) of the primary transistor (12, 22, 32, 42, 52). According to some embodiments of the invention, the secondary transistors (15, 25) have their gates biased to a bias voltage corresponding to their conductivity type. According to other embodiments, the gate of the secondary transistor (35, 45, 55) is connected to one end of its source-drain path. The disclosed arrangements provide good on-state performance while minimizing off-state source-drain leakage, and maintaining excellent transient frequency performance.

Claims

1. An integrated circuit, comprising:

a primary field-effect transistor formed in a surface of a semiconductor substrate, having a source-drain path, a gate, and a body node of a first conductivity type; and

a secondary field-effect transistor formed in the surface of the semiconductor substrate, having a source-drain path connected on one end to the gate of the primary transistor and connected on another end to the body node of the primary transistor, the secondary transistor having a gate biased so that the voltage of the body node of the primary transistor is higher when the gate of the primary transistor is at a voltage that turns on the primary transistor than when the gate of the primary transistor is at a voltage that turns off the primary transistor.

2. The integrated circuit of claim 1, wherein the body node of the secondary transistor is of the first conductivity type.

3. The integrated circuit of claim 1, wherein the body node of the secondary transistor is of a second conductivity type, opposite that of the first conductivity type.

4. The integrated circuit of claim 1, wherein the secondary transistor has a body node connected to a power supply voltage.

5. The integrated circuit of claim 1, wherein the gate of the secondary transistor is connected to one end of its source-drain path.

6. The integrated circuit of claim 5, wherein the body node of the secondary transistor is of the first conductivity type;

and wherein the gate of the secondary transistor is connected to the end of its source-drain path connected to the gate of the primary transistor.

7. The integrated circuit of claim 5, wherein the body node of the secondary transistor is of a second conductivity type, opposite that of the first conductivity type.

8. The integrated circuit of claim 1, wherein the substrate is of the first conductivity type;

and further comprising;

a well, of a second conductivity type, opposite that of the first conductivity type, surrounding the body node of the primary transistor, to provide junction isolation of the body node of the primary transistor from the substrate.

9. The integrated circuit of claim 1, wherein the primary transistor has a channel width that is substantially larger than a channel width of the secondary transistor.

10. An integrated circuit, comprising:

a primary field-effect transistor formed in a surface of a semiconductor substrate, and having a source, a drain, a gate, and a body node of a first conductivity type;

a secondary field-effect transistor formed in a surface of a semiconductor substrate, and having a source-drain path connected on one end to the gate of the primary transistor and connected on another end to the body node of the primary transistor, the secondary transistor having a gate biased to a bias voltage corresponding to its conductivity type.

11. The integrated circuit of claim 10, wherein the body node of the secondary transistor is of the first conductivity type.

12. The integrated circuit of claim 10, wherein the body node of the secondary transistor is of a second conductivity type, opposite that of the first conductivity type.

13. The integrated circuit of claim 10, wherein the secondary transistor has a body node connected to a power supply voltage.

14. The integrated circuit of claim 10, wherein the primary and secondary transistors are disposed near a surface of a substrate that is of the first conductivity type;

and further comprising;

a well, of a second conductivity type, opposite that of the first conductivity type, surrounding the body node of the primary transistor, to provide junction isolation of the body node of the primary transistor from the substrate.

15. The integrated circuit of claim 10, wherein the primary transistor has a channel width that is substantially larger than a channel width of the secondary transistor.