Intercrossedly-stacked dual-chip semiconductor package and method of fabricating the same

• US 20020096752A1
• Filed: 05/25/2001
• Published: 07/25/2002
• Est. Priority Date: 01/19/2001
• Status: Active Grant

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Huang, Chien-Ping
• Granted Patent: US 6,462,422 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: B82Y 15/00 Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/32257 the layer connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A stacked dual-chip semiconductor packaging technology is proposed for the packaging of two semiconductor chips in one single package unit. The proposed dual-chip semiconductor package is characterized by an intercrossedly-stacked dual-chip arrangement which is constructed on a specially-designed leadframe having a supporting frame; a die pad supported on the supporting frame and having a peripherally-located upper portion and a centrally-located downset portion; and a set of leads linked to the supporting frame and arranged around the die pad. By the proposed packaging technology, a first semiconductor chip is mounted within the downset portion of the die pad, while a second semiconductor chip is mounted on the upper portion of the die pad in an intercrossedly-stacked manner in relation to the first semiconductor chip. Compared to the prior art, the proposed technology allows the packaging process to be implemented in a less complex and more cost-effective manner. Moreover, since the underlying chip is attached to die pad, it allows an increased heat-dissipation efficiency to the semiconductor package.

Claims

1. A semiconductor package, which comprises:

(a) a lead-frame, which includes;

(a1) a die pad having a peripherally-located upper portion and a centrally-located downset portion,

(a2) a set of leads arranged around the die pad;

(b) a first semiconductor chip having a substantially rectangularly-shaped active surface formed with a plurality of I/O pads along the shorter sides thereof and an inactive surface adhered to the downset portion of the die pad;

(c) a second semiconductor chip having a substantially rectangularly-shaped active surface formed with a plurality of I/O pads and an inactive surface adhered to the upper portion of the die pad and above the first semiconductor chip to form an intercrossedly-stacked dual-chip arrangement;

the shorter sides of the second semiconductor chip being smaller than the longer sides of the first semiconductor chip to allow the I/O pads of the first semiconductor chip to be uncovered by the second semiconductor chip; and

(d) a set of bonding wires for electrically connecting the respective I/O pads of the first and second semiconductor chips to the leads.

2. The semiconductor package of claim 1, wherein the centrally-located downset portion is formed with at least one opening to help prevent the first semiconductor chip from delamination.

3. The semiconductor package of claim 1, wherein the centrally-located downset portion of the die pad is formed with at least one slot to help prevent the first semiconductor chip from delamination.

4. The semiconductor package of claim 1, wherein the inactive surface of the first semiconductor chip is adhered to the downset portion of the die pad by means of silver epoxy.

5. The semiconductor package of claim 1, wherein the inactive surface of the second semiconductor chip is adhered to the upper portion of the die pad by means of silver epoxy.

6. The semiconductor package of claim 1, 2 or 3, wherein the bonding wires are gold wires.

7. A method for fabricating a semiconductor package, comprising the steps of:

(1) preparing a lead-frame, which includes;

a die pad having a peripherally-located upper portion and a centrally-located downset portion; and

a set of leads arranged around the die pad;

(2) performing a first die-attachment process to mount a first semiconductor chip on the downset portion of the die pad;

the first semiconductor chip having a substantially rectangularly-shaped active surface formed with a plurality of I/O pads along the shorter sides thereof and an inactive surface adhered to the centrally-located downset portion of the die pad,

(3) performing a first wire-bonding pricess to bond a set of bonding wires for electrically connecting the respective I/O pads of the first semiconductor chip to the corresponding leads;

(4) performing a second die-attachment process to mount a second semiconductor chip on the die pad;

the second semiconductor chip having an active surface formed with a plurality of I/O pads and an inactive surface adhered to the upper portion of the die pad so as to form an intercrossedly-stacked dual-chip arrangement with the first semiconductor chip; and

(5) performing a second wire-bonding process to bond a set of bonding wires for electrically connecting the respective I/O pads of the second semiconductor chip to the corresponding leads.

8. The semiconductor package of claim 7, wherein in said step (1), the centrally-located downset portion of the die pad is further formed with at least one opening to help prevent the first semiconductor chip from delamination.

9. The semiconductor package of claim 7, wherein in said step (1), the centrally-located downset portion of the die pad is further formed with at least one slot to help prevent the first semiconductor chi from delamination.

10. The semiconductor package of claim 7, 8 or 9, wherein in said step (2), the inactive surface of the first semiconductor chip is adhered to the downset portion of the die pad by means of silver epoxy.

11. The semiconductor package of claim 7, 8 or 9, wherein in said step (3), the inactive surface of the second semiconductor chip is adhered to the upper portion of the die pad by means of silver epoxy.

12. The semiconductor package of claim 7, 8 or 9, wherein in said step (3) and (15), the bonding wires are gold wires.

14. The semiconductor package of claim 13, wherein in said step (3), the inactive surface of the first semiconductor chip is adhered to the downset portion of the die pad by means of silver epoxy.

15. The semiconductor package of claim 13, wherein in said step (5), the inactive surface of the second semiconductor chip is adhered to the upper portion of the die pad by means of silver epoxy.

16. The semiconductor package of claim 13, wherein in said step (4) and (6), the bonding wires are gold wires.

17. The semiconductor package of claim 13, wherein the opening on the downset portion of the die pad is a slot.

13. A method for fabricating a semiconductor package, comprising the steps of:

(1) preparing a lead-frame, which includes;

a die pad having a peripherally-located upper portion and a centrally-located downset portion;

a set of leads arranged around the die pad;

(2) forming at least one opening in the downset portion of the die pad;

(3) performing a first die-attachment process to mount a first semiconductor chip on the downset portion of the die pad,

the first semiconductor chip having an active surface formed with a plurality of I/O pads and an inactive surface adhered to the centrally-located downset portion of the die pad;

(4) performing a first wire-bonding process to bond a set of bonding wires for electrically connecting the respective I/O pads of the first semiconductor chip to the corresponding leads;

(5) performing a second die-attachment process to mount a second semiconductor chip on the upper portion of the die pad;

the second semiconductor chip having an active surface formed with a plurality of I/O pads and an inactive surface adhered to the upper portion of the die pad, and being located above the first semiconductor chip to form an intercrossedly stacked dual-chip arrangement; and

(6) performing a second wire-bonding process to bond a set of bonding wires for electrically connecting the respective I/O pads of the second semiconductor chip to the leads.