Semiconductor assembly encapsulation mold

• US 20020096789A1
• Filed: 01/23/2001
• Published: 07/25/2002
• Est. Priority Date: 01/23/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bolken, Todd O.
• Granted Patent: US 6,734,571 B2
• Time in Patent Office: Days
• US Class Current: 257/787
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An encapsulation mold for forming an encapsulation layer over a semiconductor assembly is disclosed. A semiconductor assembly with multiple semiconductor dies secured to a single semiconductor support structure is inserted into an encapsulation mold. The mold contains a first section and a second section, which form a cavity around the assembly. The mold contains an aperture for transferring encapsulating material into the mold cavity. One of the mold sections has a design feature, such as a raised rib or groove interconnecting at approximately the separation or saw-cut regions of the individual dies of the assembly. Encapsulation material is inserted into the mold cavity until the cavity is filled. The mold section design feature shapes the top surface of the encapsulation layer. The mold is removed leaving the exterior surface of the encapsulation layer patterned with the design feature. The assembly is then separated into individual dies along the design feature boundary of the encapsulation layer'"'"'s exterior surface.

Claims

1. A semiconductor assembly encapsulation mold comprising:

a first mold section; and

a second mold section, said first and second mold sections being engagable and shaped to define a cavity for molding a semiconductor assembly comprising a substrate and a plurality of dies supported by said substrate, one of said mold sections having an interior surface which faces a semiconductor assembly placed in said mold, said interior surface having a design feature which produces a complementary design feature in an exterior surface of an encapsulation layer covering said semiconductor assembly at locations between dies of said assembly.

2. The semiconductor assembly encapsulation mold of claim 1, wherein the said second mold section design feature projects into said mold cavity.

3. The semiconductor assembly encapsulation mold of claim 2, wherein said second mold section design feature has straight sides.

4. The semiconductor assembly encapsulation mold of claim 2, wherein said second mold section design feature has sloped sides.

5. The semiconductor assembly encapsulation mold of claim 2, wherein said second mold section design feature has curved sides.

6. The semiconductor assembly encapsulation mold of claim 1, wherein said second mold section design feature projects outside said mold cavity.

7. The semiconductor assembly encapsulation mold of claim 6, wherein said second mold section design feature has straight sides.

8. The semiconductor assembly encapsulation mold of claim 6, wherein said mold section design feature has sloped sides.

9. The semiconductor assembly encapsulation mold of claim 6, wherein said second mold section design feature has curved sides.

10. The semiconductor assembly encapsulation mold of claim 2, wherein said second mold section design feature produces an interconnected series of cavities on said exterior surface of said encapsulation layer of said semiconductor assembly.

11. The semiconductor assembly encapsulation mold of claim 2, wherein said design feature is about 10 microns or greater from said plurality of dies.

12. The semiconductor assembly encapsulation mold of claim 2, wherein said design feature has a width of about 0.15 microns or greater.

13. The semiconductor assembly encapsulation mold of claim 6, wherein said second mold section design feature produces an interconnected raised riblet design feature on said exterior surface of said encapsulation layer of said semiconductor assembly.

15. A semiconductor assembly of claim 14, wherein said design feature projects into said encapsulation layer exterior surface.

16. The semiconductor assembly of claim 15, wherein said design feature has straight sides.

17. The semiconductor assembly of claim 15, wherein said design feature has sloped sides.

18. The semiconductor assembly of claim 15, wherein said design feature has curved sides.

19. The semiconductor assembly of claim 15, wherein said encapsulation layer exterior surface comprises an interconnected series of cavities.

20. The semiconductor assembly of claim 15, wherein said encapsulation layer exterior surface is about 10 microns or greater above said plurality of dies.

21. The semiconductor assembly of claim 15, wherein said design feature has a width of about 0.15 microns or greater.

22. The semiconductor assembly of claim 14, wherein said design feature projects out from said encapsulation layer exterior surface.

23. The semiconductor assembly of claim 22, wherein said design feature has straight sides.

24. The semiconductor assembly of claim 22, wherein said design feature has sloped sides.

25. The semiconductor assembly of claim 22, wherein said design feature has curved sides.

26. The semiconductor assembly of claim 22, wherein said encapsulation layer exterior surface comprises an interconnected series of raised ribs.

27. The semiconductor assembly of claim 14, wherein said support structure is a printed circuit board.

28. The semiconductor assembly of claim 14, wherein said encapsulating material comprises plastic.

29. The semiconductor assembly of claim 14, wherein said encapsulating material comprises molded epoxy compound.

30. The semiconductor assembly of claim 14, wherein said encapsulating material comprises resin.

14. A semiconductor assembly comprising:

a semiconductor die support structure having a top and a bottom surface,

a plurality of semiconductor dies secured to said support structure top surface; and

an encapsulation layer having an exterior surface and covering said at least two semiconductor dies and said support structure top surface, is wherein said encapsulation layer exterior surface has one of a raised or lowered design feature at locations between said plurality of dies of said assembly.

31. A method of forming an semiconductor assembly encapsulation mold comprising:

forming a first mold section; and

forming a second mold section having a top surface, and one of said mold sections having an interior surface, said interior surface having a design feature which produces a complementary design feature in an exterior surface in an encapsulation layer of a semiconductor assembly at locations between a plurality of dies on said assembly.

32. The method of claim 31, wherein said design feature projects into a mold cavity formed by securing said mold sections to each other.

33. The method of claim 32, wherein said design feature produces an interconnected series of cavities on said exterior surface of said encapsulation layer of said semiconductor assembly.

34. The method of claim 31, wherein said design feature projects out from a mold cavity formed by securing said mold sections to each other.

35. The method of claim 34, wherein said design feature produces an interconnected raised riblet on said exterior surface of said encapsulation layer of said semiconductor assembly.

37. The method of claim 36, wherein said mold interior surface has one of a raised or lowered design feature at locations between said plurality of dies of said assembly.

36. A method of encapsulating a semiconductor assembly comprising:

providing a semiconductor assembly comprising a semiconductor die support structure having a top and a bottom surface and a plurality of semiconductor die secured to said top surface of said support structure;

inserting said assembly into an encapsulation mold, said mold having a first mold section and a second mold section, and one of said mold sections having an interior surface, said interior surface having a design feature which produces a complementary design feature in an exterior surface in an encapsulation layer of a semiconductor assembly at locations between a plurality of dies on said assembly; and

transferring encapsulating material into a cavity formed by said first and second mold section.