Balun transformer for a satellite television tuner

• US 20020097107A1
• Filed: 06/28/2001
• Published: 07/25/2002
• Est. Priority Date: 01/22/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Burns, Lawrence M., Pobanz, Carl W.
• Granted Patent: US 6,819,199 B2
• Time in Patent Office: Days
• US Class Current: 333/26
• CPC Class Codes: H01P 5/10 for coupling balanced lines or devices with unbalanced lines or devices
• CPC Class Codes: H05K 1/0239 Signal transmission by AC coupling
• CPC Class Codes: H05K 2201/10015 Non-printed capacitor

Abstract

The invention is a balun transformer that converts a single-ended (or unbalanced) signal to a differential (or balanced) signal. The balun is a printed metal pattern on a circuit board in conjunction with several low cost chip capacitors and a low cost chip inductor. The balun transformer is a modified Marchand balun that is implemented using printed transmission lines. The balun has a plurality of coupled transmission lines to improve tolerances to variations in PC board fabrication. To make the balun compact, it is electrically lengthened through the use of capacitive loading, which reduces the required physical size. Additionally, the capacitors increase the bandwidth due to the resonant interaction between the short inductive balun and the capacitors that are placed in series with the input and the output.

Claims

1. A balun, comprising:

a first capacitor coupled to an input;

a plurality of first coupled metal traces coupled to said first capacitor;

a plurality of second coupled metal traces, said second coupled metal traces electromagnetically coupled to said first coupled metal traces;

a ground coupled to said second coupled metal traces;

a first output coupled to said second coupled metal traces;

a second output coupled to said second coupled metal traces;

a second capacitor coupled between said first coupled metal traces and said ground;

a third capacitor coupled to said first output; and

a fourth capacitor coupled to said second output.

2. The balun of claim 1, wherein said first coupled metal traces and said second coupled metal traces are located on a surface layer of a printed circuit board.

3. The balun of claim 1, wherein said first coupled metal traces and said second coupled metal traces are located on the same layer of a printed circuit board.

4. The balun of claim 1, wherein said ground is placed beneath said first coupled metal traces and said second coupled metal traces.

5. The balun of claim 1, wherein said ground is placed at a periphery of said first coupled metal traces and said second coupled metal traces.

6. The balun of claim 1, further comprising:

a fifth capacitor coupled between said first output and said second output.

7. The balun of claim 1, wherein said first output provides a signal having an equal amplitude and opposite phase to a signal provided from said second output in response to a signal input to said input.

8. The balun of claim 1, wherein said first coupled metal traces and said second coupled metal traces are transmission lines.

9. The balun of claim 8, wherein said plurality of first coupled transmission lines comprises one first coupled transmission line or two first coupled transmission lines.

10. The balun of claim 8, wherein a longitudinal dimension of said transmission lines is less than one-quarter wavelength of said input signal.

11. The balun of claim 8, wherein said transmission lines are coplanar waveguide transmission lines or microstrip transmission lines.

12. The balun of claim 1, further comprising a first impedance matching network coupled to said input and a second impedance matching network coupled to said first output and said second output.

13. The balun of claim 12, wherein said first impedance matching network comprises a fifth capacitor series coupled to an inductor.

14. The balun of claim 12, wherein said second impedance matching network comprises:

two coupled metal traces, wherein at least one of a metal trace width, a metal trace spacing and a metal trace thickness is adjusted to provide a desired output impedance.

15. The balun of claim 14, wherein said second impedance matching network comprises lumped element components.

16. The balun of claim 12, wherein an input impedance of said balun is approximately 50 to 75 ohms.

17. The balun of claim 12, wherein the output impedance of said balun is a desired value.

18. The balun of claim 1, wherein a direct current power and low frequency digital control signal source is coupled to said input.

19. The balun of claim 18, wherein a metal trace is coupled between said direct current power and low frequency digital control signal source and said input, wherein said metal trace does not effect said balun'"'"'s electrical characteristics over a desired frequency range.

20. The balun of claim 19, wherein said metal trace is a spiral inductor.

21. The balun of claim 20, wherein said inductor is coupled to said input approximately 425 mils from said input.

22. A balun comprising:

a plurality of coupled metal traces;

an input, coupled to said metal traces;

an output, coupled to said metal traces,

means for producing output signals having an equal amplitude and opposite phase responsive to an input signal received at said input, and

means for reducing a physical dimension of said metal traces.

23. The balun of claim 22, further comprising:

means for applying direct current power and low frequency digital control signals to said metal traces without electrically loading said balun over a desired frequency band.

24. The balun of claim 23, wherein said desired frequency range is approximately 950 to 2150 megahertz.

26. The integrated circuit of claim 25, further comprising:

a metal trace coupled to said electrically unbalanced input, said metal trace having a high impedance to an input signal over a desired frequency range.

27. The integrated circuit of claim 25, wherein said metal trace is a spiral inductor.

28. The integrated circuit of claim 25, wherein said desired frequency range is approximately 950 to 2150 megahertz.

30. The method of claim 29, wherein step 1 comprises the following steps:

(a) selecting an initial metal trace length, an initial metal trace spacing, and an initial metal trace spacing;

(b) selecting an initial balun size and trace layout, wherein said initial balun size and trace layout are a function of step (a);

(c) selecting an initial ground plane configuration; and

(d) selecting an initial capacitor value.

31. The method of claim 29, wherein step 2 comprises the following steps:

(a) encoding said balun parameters in a simulator;

(b) driving said balun with an input circuit having a characteristic input impedance;

(c) loading said balun with a substantially balanced differential load; and

(d) calculating passband insertion loss, input return loss, bandwidth, and differential signal balance based on steps (a) through (c).

32. The method of claim 29, wherein step 4 comprises the following steps:

(a) varying a value of a capacitor incrementally;

(b) varying a length of a printed metal trace incrementally;

(c) varying a width of said printed trace incrementally; and

(d) varying a spacing of said printed trace incrementally, wherein said varying is selected to result in balun performance closer to a design goal.

33. The method of claim 32, wherein step 4 further comprises:

(e) adjusting the symmetry of said balun by incrementally varying the lengths of said metal traces on one side of the balun.

34. The method of claim 29, wherein step 5 further comprises:

(a) adding an actual load impedance to a simulator;

(b) adding an input impedance matching network to said balun;

(c) adding an output impedance matching network to said balun;

(d) simulating a balun performance;

(e) comparing said performance to said design goal;

(f) incrementally varying at least one component of said input and said output impedance matching networks, wherein said varying step is performed to move said balun performance closer to a design goal; and

(g) performing said simulating and said comparing steps until said simulated balun performance is equal to or better than said design goal performance.

25. An integrated circuit, comprising:

a capacitively loaded balun;

a first circuit, coupled to an electrically unbalanced input of said capacitively loaded balun;

a second circuit, coupled to an electrically balanced output of said capacitively loaded balun;

wherein said electrically unbalanced input is impedance matched to said first circuit and said electrically balanced electrical output is impedance matched to said second circuit.

29. A method of designing an improved printed trace balun, comprising the steps of:

(1) selecting balun design parameters;

(2) simulating said balun performance;

(3) comparing said simulated performance with a design goal performance;

(4) incrementally varying said balun design parameters; and

(5) repeating steps 2 through 4 until said simulated balun performance is equal or better than design goal performance.